MCIMX6U5EVM10AB Freescale Semiconductor, MCIMX6U5EVM10AB Datasheet - Page 79

• Manufacturer Part Number: MCIMX6U5EVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

1
2
3
4
5
6
Freescale Semiconductor
No.
81
82
83
84
86
87
89
90
91
95
96
97
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
SCKT rising edge to FST out (wr) low
SCKT rising edge to FST out (wl) high
SCKT rising edge to FST out (wl) low
SCKT rising edge to data out enable from high
impedance
SCKT rising edge to data out valid
SCKT rising edge to data out high impedance
FST input (bl, wr) setup time before SCKT falling edge
FST input (wl) setup time before SCKT falling edge
FST input hold time after SCKT falling edge
HCKR/HCKT clock cycle
HCKT input rising edge to SCKT output
HCKR input rising edge to SCKR output
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Table 52. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics
1,2
5
67
5
Symbol
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Expression
2 x T
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
2
18.0
18.0
Min
2.0
2.0
4.0
5.0
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Electrical Characteristics
Max
22.0
12.0
19.0
20.0
10.0
22.0
17.0
18.0
13.0
21.0
16.0
18.0
18.0
9.0
—
—
—
—
—
—
—
Condition
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
—
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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