MCIMX6U5EVM10AB Freescale Semiconductor, MCIMX6U5EVM10AB Datasheet - Page 16

• Manufacturer Part Number: MCIMX6U5EVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

Modules List
16
Block Mnemonic
SDMA
SPDIF
SNVS
SJC
System JTAG Controller
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Smart Direct Memory
Interconnect Format
Secure Non-Volatile
Sony Philips Digital
Block Name
Storage
Access
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
System Control
System Control
Subsystem
Peripherals
Peripherals
Peripherals
Multimedia
Security
The SDMA is multi-channel flexible DMA engine. It
helps in maximizing system performance by off-loading
the various cores in dynamic data routing. It has the
following features:
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
6Solo/6DualLite processors use JTAG port for
production, testing, and system debugging. In addition,
the SJC provides BSR (Boundary Scan Register)
standard support, which complies with IEEE1149.1 and
IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6Solo/6DualLite SJC
incorporates three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
• Powered by a 16-bit Instruction-Set micro-RISC
• Multi-channel DMA supporting up to 32 time-division
• 48 events with total flexibility to trigger any
• Memory accesses including linear, FIFO, and 2D
• Shared peripherals between ARM and SDMA
• Very fast Context-Switching with 2-level priority
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
• DMA ports can handle unit-directional and
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
engine
multiplexed DMA channels
combination of channels
addressing
based preemptive multi-tasking
(increment, decrement, and no address changes on
source and destination address)
bi-directional flows (copy mode)
Brief Description
Freescale Semiconductor