C8051F989-GUR Silicon Labs, C8051F989-GUR Datasheet - Page 73
C8051F989-GUR
Manufacturer Part Number
C8051F989-GUR
Description
8-bit Microcontrollers - MCU 4kB 512B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F989-GUR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 73 of 322
- Download datasheet (2Mb)
SFR Definition 5.2. ADC0CF: ADC0 Configuration
SFR Page = 0x0; SFR Address = 0x97
Name
Reset
Bit
Type
7:3
2
1
0
Bit
AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
AMP0GN
AD08BE
AD0TM
Name
7
1
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.10.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
*Round the result up.
AD0SC
CLK
6
1
SAR
=
=
AD0SC[4:0]
------------------- - 1
CLK
or
FCLK
----------------------------
AD0SC
R/W
5
1
FCLK
SAR
–
+
1
*
Rev. 1.1
4
1
C8051F99x-C8051F98x
Function
3
1
AD08BE
R/W
2
0
AD0TM
R/W
1
0
AMP0GN
R/W
0
0
73
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