AT26F004-MU Atmel, AT26F004-MU Datasheet - Page 12
![IC FLASH 4MBIT 33MHZ 8QFN](/photos/7/26/72647/8-vfqfn-8m1-a_sml.jpg)
AT26F004-MU
Manufacturer Part Number
AT26F004-MU
Description
IC FLASH 4MBIT 33MHZ 8QFN
Manufacturer
Atmel
Datasheet
1.AT26F004-MU.pdf
(38 pages)
Specifications of AT26F004-MU
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
4M (2048 pages x 256 bytes)
Speed
33MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT26F004-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8.4
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,
the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of t
.
CHPE
The complete opcode must be clocked into the device before the CS pin is deasserted; other-
wise, no erase will be performed. In addition, if any sector of the memory array is in the
protected state, then the Chip Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be
reset back to the logical “0” state if a sector is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the t
time to determine if the device has finished erasing. At
CHPE
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
Figure 8-5.
Chip Erase
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
C
C
C
C
C
C
C
C
MSB
HIGH-IMPEDANCE
SO
AT26F004
12
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