ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 160
![no-image](/images/no-image-200.jpg)
ZLF645S0Q2032G
Manufacturer Part Number
ZLF645S0Q2032G
Description
8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
Manufacturer
Maxim Integrated
Datasheet
1.ZLF645E0H4864G2204.pdf
(201 pages)
Specifications of ZLF645S0Q2032G
Core
Z8
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
32 KB
Data Ram Size
1 KB
On-chip Adc
No
Operating Supply Voltage
2 V to 3.6 V
Package / Case
QFN-EP-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Number Of Programmable I/os
5
Number Of Timers
2 x 8 bit, 1 x 16 bit
On-chip Dac
No
Processor Series
ZLF645
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2 V
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Table 71. Stop Mode Recovery Register 2 (SMR2)
19-4572; Rev 0; 4/09
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[6]
[5]
[4:2]
[1:0]
Note:
SMR3 Register Events
Reserved
Value
This register is not reset after a Stop Mode Recovery.
The SMR3 register can be used to configure one or more of Port 3, pins 0–3 to be
compared to a written or sampled reference value and generate a Stop Mode Recovery
event when the pin state differs from the reference value.
000
001
010
011
100
101
110
111
—
—
—
—
X
0
1
7
Description
Reserved —Read is undefined; write must be 0.
Stop Mode Recovery Level 2
Selects whether an SMR2[4:2]-selected SMR is initiated by a Low or High level at
the XOR-gate input (see
Low.
High.
Reserved —Read is undefined; Must be written to 1.
Stop Mode Recovery Source
Specifies a Stop Mode Recovery wake-up source at th e XOR gate input (see
Figure 46
SMR3 registers. If more than one source is selected, any selected source event
causes a Stop Mode Recover y. The following equations ignore any Port pin that
is selected in register SMR1 or configured as an output.
No SMR2 register source selected.
NAND of P23:P20.
NAND of P27:P20.
NOR of P33:P31.
NAND of P33:P31.
NOR of P33:P31, P00, P07.
NAND of P33:P31, P00, P07.
NAND of P33:P31, P22:P20.
Reserved —Read is undefined; write must be 00b.
Stop Mode Recovery
Level 2
on page 151). Additional sources can be selected by SMR, SMR1, and
W
6
0
Bank F: 0Dh; Linear: F0Dh
Figure 46
Reserved
—
X
5
on page 151).
W
4
Stop Mode Recovery
0
Source
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
W
3
0
Product Specification
W
2
0
Reserved
X
1
—
X
0
152
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