ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 182

• Manufacturer Part Number: ZLF645S0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

Table 85. User Option Byte 1 (OPT1)
19-4572; Rev 0; 4/09
Bit
Field
Erased State
Flash Address
Bit Position
[7:4]
[3]
[2]
[1]
Value
—
1
0
1
0
1
0
7
1
Description
Reserved
16BITSTK —16 bit Stack Pointer Addressiblity Enable
The ZLF645 is enabled for 8-bits of stack pointer addressiblity allowing usage
of Bank 0 only of the devices general-purpose RAM space as the CPU stack.
The ZLF645 is enabled for 16-bits of stack pointer addressiblity allowing usage
of all of the devices general-purpose RAM space as the CPU stack.
DIVBY1 —System Clock Divide By 1 Enable
If SMR register bit 0 is also programmed to 0, the system clock frequency is
equal to the external clock frequency input on the XTAL1 pin divided by 2.
If SMR register bit 0 is also programmed to 0, the system clock frequency is
equal to the external clock frequency input on the XTAL1 pin.
FLPROT1 —Flash Main Memory Lower Half Protect
The Flash main memory and all of Information Area Page 3 can be read,
written, and erased by both the Flash Byte Programming interface or through
the ICP interface as long as FLRWP is also 1.
Reads and Writes to the lower half of Flash main memory and writes and
erasures to Information Area Page 3, by the ICP or Flash Byte Programming
interfaces is disabled unless, with this bit 0, a main memory mass erase is
completed first. A main memory mass erase causes resetting of this bit value
in the Option Byte 1 shadow register to a 1 but does not effect the
corresponding Flash memory bit. Once the Option Byte 1 shadow register bit
is reset, the ICP or Flash Byte Programming interface is allowed full read,
write, and erase access to the Flash's main memory and to Page 3 of the
Information Area and can reset the corresponding Flash memory bit.
6
1
Reserved
—
Flash Memory Information Area address: FFH
Must be written 1.
5
1
4
1
16BITSTK DIVBY1 FLPROT1
3
1
ZLF645 Series Flash MCUs
1
2
Product Specification
1
1
FLRWP
Operation
0
1
174