ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 53

• Manufacturer Part Number: ZLF645S0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

PS026408-1208
Register Pointer Example
Linear Memory Addressing
R253 RP = 00h
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
R4 = Port 4
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
R4 = TC8L
The counter/timers are mapped into ERF Group D. Access is easily performed using the
following code segment:
LD RP, #0Dh
LD R0,#xx
LD 1, #xx
LD R1, 2
LD RP, #7Dh
LD 71h, 2
LD R1, 2
In addition to using the RP register to designate a bank and working register group for
8-bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in
any other bank to or from a register in the current bank. Linear addressing is implemented
through the LDX and LDXI instructions only. Linear addressing treats the register file as
if all the registers are logically ordered end-to-end, as opposed to being grouped into
banks and working register groups, as displayed in
addressing, register file addresses are numbered sequentially from Bank 0, register 00h to
Bank 0, register FFh, then continuing with Bank 1, register 00h, and so on up to Bank F,
register FFh.
Using the LDX and/or the LDXI instructions, either the target or destination register
location can be addressed through a 12-bit linear address value stored in a general-purpose
register pair.
; Select ERF D for access to Bank D
; (working register group 0)
; load CTR0
; load CTR1
; CTR2 CTR1
; Select Expanded Register Bank D and working
; register group 7 of Bank 0 for access.
; CTR2 register 71h
; CTR2 register 71h
Figure 15
ZLF645 Series Flash MCUs
Product Specification
on page 47. For linear
Register File
45