ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 181

• Manufacturer Part Number: ZLF645S0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

Table 84. User Option Byte 0 Shadow Register (OPT0SR)
19-4572; Rev 0; 4/09
Bit
Field
Reset State
CPU Access (R/W)
Register Address (R/W)
Note:
Note:
User Option Byte 1 and Option Byte 1 Shadow Register 
Definitions
User Option byte allows the enabling of various features including protecting the Flash’s
main memory from read operations through either of the ZLF645’s Flash access inter-
faces. For it’s associated shadow registers, until the registers are loaded with their corre-
sponding option bit values, their outputs will be in an unknown state.
Table 85
This byte can be programmed and erased (by Page 3 erase) only through the ICP.
During device Power-on Reset, bit 1 and bit 0 value of this Flash Option byte are sampled
into flip-flops, whose outputs control the Flash memory protect function. User codes can
read the flip-flop values, by reading from a uniquely assigned peripheral register address.
User codes cannot over-write the flip-flop values to change this Flash memory protect
function.
describes User Option byte 1 function.
P2PU = 1: Port 2 Pull-ups disabled. 
P2PU = 0: Port 2 Pull-ups enabled.
P1HPU = 1: Port 1 high nibble Pull-ups disabled 
P1HPU = 0: Port 1 high nibble Pull-ups enabled.
P1LPU = 1: Port 1 low nibble Pull-ups disabled. 
P1LPU = 0: Port 1 low nibble Pull-ups enabled.
P0HPU = 1: Port 0 high nibble Pull-ups disabled. 
P0HPU = 0: Port 0 high nibble Pull-ups enabled.
P0LPU = 1: Port 0 low nibble Pull-ups disabled. 
P0LPU = 0: Port 0 low nibble Pull-ups enabled.
WDT
R/W
X
7
P4PU
R/W
6
X
P3PU
R/W
X
5
Bank D: 0Eh; Linear: D0Eh
P2PU
R/W
X
4
P1HPU P1LPU
R/W
X
3
ZLF645 Series Flash MCUs
R/W
Product Specification
X
2
P0HPU
R/W
X
1
Operation
P0LPU
R/W
X
0
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