C8051F045R Silicon Labs, C8051F045R Datasheet - Page 127

• Manufacturer Part Number: C8051F045R
• Description: 8-bit Microcontrollers - MCU 25 MIPS 64KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F045R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Data Rom Size: 64 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

12. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
five 16-bit counter/timers (see description in
tion 21
space (see
includes on-chip debug hardware (see description in
analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).
The CIP-51 includes the following features:
-
-
-
-
-
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
8/4 Byte-Wide I/O Ports
and
Section
Section
12.2.6), and 8/4 byte-wide I/O Ports (see description in
22), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address
RESET
CLOCK
STOP
IDLE
Figure 12.1. CIP-51 Block Diagram
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
Section
ALU
Rev. 1.5
TMP2
DATA BUS
DATA BUS
D8
D8
D8
Section
23), two full-duplex UARTs (see description in
-
-
-
-
-
C8051F040/1/2/3/4/5/6/7
A16
D8
D8
D8
D8
B REGISTER
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
REGISTER
INTERRUPT
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
25), and interfaces directly with the MCUs'
SFR
BUS
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
DEBUG_IRQ
Section
17). The CIP-51 also
Sec-
127