C8051F045R Silicon Labs, C8051F045R Datasheet - Page 241
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C8051F045R
Manufacturer Part Number
C8051F045R
Description
8-bit Microcontrollers - MCU 25 MIPS 64KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F044R.pdf
(328 pages)
Specifications of C8051F045R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
13
Data Rom Size
64 KB
Interface Type
CAN, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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19.2. SMBus Protocol
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. Note:
multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitra-
tion. Note that it is not necessary to specify one device as the master in a system; any device who trans-
mits a START and a slave address becomes the master for that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 19.3). If the receiving device does not ACK, the transmitting device will read a “not acknowledge”
(NACK), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to
logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data one byte at a time
and expects an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data and expects an ACK from the master at the end of each byte. At the end of the data transfer, the mas-
ter generates a STOP condition to terminate the transaction and free the bus. Figure 19.3 illustrates a typ-
ical SMBus transaction.
19.2.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see
attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give
up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a
LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect
a LOW SDA and give up the bus. The winning master continues its transmission without interruption; the
losing master becomes a slave and receives the rest of the transfer. This arbitration scheme is non-
destructive: one device always wins, and no data is lost.
SCL
SDA
START
SLA6
Slave Address + R/W
Figure 19.3. SMBus Transaction
SLA5-0
R/W
Rev. 1.5
Section
ACK
C8051F040/1/2/3/4/5/6/7
19.2.4). In the event that two or more devices
D7
Data Byte
D6-0
NACK
STOP
241
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