MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 10

• Manufacturer Part Number: MT48H4M16LFB4-8:H
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-8:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Burst Type
Table 4:
CAS Latency (CL)
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Length
Burst
2
4
8
Burst Definition
Starting Column Address
A2
0
0
0
0
1
1
1
1
by A1–A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when
BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block.
Accesses within a given burst may be programmed to be sequential or interleaved; this is
referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4.
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in Figure 5 on page 11. Table 5 on page 14 indicates the
operating frequencies at which each CL setting can be used.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
10
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Order of Accesses within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
Mode Register Definition
Type = Interleaved
©2006 Micron Technology, Inc. All rights reserved.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0