MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 21

• Manufacturer Part Number: MT48H4M16LFB4-8:H
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-8:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Random READ Accesses
Note:
Note:
The DQM input is used to avoid I/O contention, as shown in Figure 12 on page 22 and
Figure 13 on page 22. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. After the WRITE command is registered, the DQ will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 14 on page 23, then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on
page 22 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 14 on page 23 shows the case where the
additional NOP is needed. A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided that auto precharge was not
activated). The PRECHARGE command should be issued x cycles before the clock edge
at which the last desired data element is valid, where x equals the CL minus one. This is
shown in Figure 14 for each possible CL; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until
Command
Command
Address
Address
Part of the row precharge time is hidden during the access of the last data element(s).
Each READ command may be issued to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
Bank,
T0
Bank,
Col n
Col n
READ
READ
CL = 2
T1
T1
Bank,
Bank,
READ
Col a
READ
Col a
CL = 3
T2
T2
Bank,
Col x
Bank,
READ
READ
Col x
D
OUT
n
21
Transitioning Data
T3
T3
Col m
Bank,
READ
READ
Bank,
Col m
D
D
OUT
a
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
T4
NOP
NOP
D
D
OUT
OUT
x
a
64Mb: 4 Meg x 16 Mobile SDRAM
T5
T5
NOP
NOP
D
D
m
OUT
OUT
x
Don’t Care
T6
NOP
t
D
RP is met.
OUT
m
©2006 Micron Technology, Inc. All rights reserved.
Operations