MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 60

IC SDRAM 64MBIT 125MHZ 54VFBGA

MT48H4M16LFB4-8:H

Manufacturer Part Number
MT48H4M16LFB4-8:H
Description
IC SDRAM 64MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H4M16LFB4-8:H

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
64M (4M x 16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
8/6ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48H4M16LFB4-8:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H4M16LFB4-8:H
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT48H4M16LFB4-8:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 47:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
A0–A9, A11
Command
BA0, BA1
DQM
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Row
Row
Bank 0
T0
Alternating Bank Write Accesses
t CKH
t CMH
t AH
t AH
t AH
t RCD - Bank 0
t RAS - Bank 0
t
t
Notes:
RC - Bank 0
RRD
t CK
T1
NOP
1. For this example, the BL = 4.
2. A8, A9, and A11 = “Don’t Care.”
Enable auto precharge
t CMS
t CL
t DS
Column m 2
Bank 0
WRITE
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
ACTIVE
Row
Bank 1
Row
IN
T4
m + 2
t DH
60
t RCD - Bank 1
t DS
D
IN
T5
NOP
m + 3
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WR - Bank 0
Enable auto precharge
64Mb: 4 Meg x 16 Mobile SDRAM
t DS
Column b 2
WRITE
Bank 1
T6
D
IN
t DH
b
t DS
t RP - Bank 0
D
NOP
IN
T7
b + 1
t DH
©2006 Micron Technology, Inc. All rights reserved.
t DS
D
Timing Diagrams
IN
NOP
T8
b + 2
t DH
t DS
D
Bank 0
Row
Row
ACTIVE
T9
IN
b + 3
t
t
RCD - Bank 0
WR - Bank 1
Don’t Care
t DH

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