MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 23

IC SDRAM 64MBIT 125MHZ 54VFBGA

MT48H4M16LFB4-8:H

Manufacturer Part Number
MT48H4M16LFB4-8:H
Description
IC SDRAM 64MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H4M16LFB4-8:H

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
64M (4M x 16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
8/6ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48H4M16LFB4-8:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H4M16LFB4-8:H
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT48H4M16LFB4-8:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 14:
Figure 15:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
READ-to-PRECHARGE
Terminating a READ Burst
Note:
Note:
Command
Command
Command
Command
Address
Address
Address
Address
CLK
CLK
CLK
CLK
DQM is LOW.
DQM is LOW.
DQ
DQ
DQ
DQ
Bank a,
Bank a,
T0
T0
T0
Bank,
T0
Col n
Col n
Col n
READ
READ
Bank,
READ
READ
Col n
CL = 2
CL = 2
CL = 3
CL = 3
T1
T1
T1
T1
NOP
NOP
NOP
NOP
T2
T2
T2
T2
NOP
NOP
NOP
NOP
D
D
OUT
OUT
n
n
T3
T3
T3
T3
Transitioning Data
NOP
NOP
NOP
NOP
23
n + 1
D
n + 1
D
D
D
OUT
OUT
n
OUT
OUT
n
Transitioning Data
PRECHARGE
PRECHARGE
TERMINATE
TERMINATE
(a or all)
(a or all)
T4
T4
T4
BURST
T4
BURST
Bank
Bank
X = 1 cycle
X = 1 cycle
n + 2
n + 2
D
D
n + 1
n + 1
D
D
OUT
OUT
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
X = 2 cycles
T5
T5
T5
T5
NOP
NOP
NOP
NOP
n + 3
n + 2
n + 3
n + 2
D
D
D
D
OUT
OUT
OUT
OUT
64Mb: 4 Meg x 16 Mobile SDRAM
t RP
t RP
T6
T6
T6
T6
NOP
NOP
NOP
NOP
n + 3
n + 3
D
D
OUT
OUT
Don’t Care
Don’t Care
Bank a,
Bank a,
ACTIVE
ACTIVE
T7
T7
T7
NOP
Row
Row
©2006 Micron Technology, Inc. All rights reserved.
Operations

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