MT48H4M16LFB4-8:H Micron Technology Inc, MT48H4M16LFB4-8:H Datasheet - Page 34

• Manufacturer Part Number: MT48H4M16LFB4-8:H
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-8:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
CKE
H
H
L
L
n - 1
CKE
H
H
Truth Table 2 – CKE
Notes: 1–4; notes appear below table
L
L
n
Notes:
Reading or writing
Deep power-down
Deep power-down
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
All banks idle
Power-down
Power-down
Self refresh
Self refresh
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state when
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is
clock edge.
MAND
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
n
is the logic state of CKE at clock edge n; CKE
n
.
t
n
XSR period. A minimum of two NOP commands must be provided during
is the command registered at clock edge n, and ACTION
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Table 7 on page 35
BURST TERMINATE
AUTO REFRESH
Command
VALID
34
X
X
X
X
X
X
t
CKS is met).
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
n - 1
Maintain deep power-down
Deep power-down entry
Maintain clock suspend
Exit deep power-down
Maintain power-down
was the state of CKE at the previous
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Self refresh entry
Exit power-down
Exit self refresh
Action
©2006 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Operations
Notes
t
XSR is
t
8
5
8
6
7
8
XSR