MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 39

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 19:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Consecutive READ Bursts
Notes:
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal
6. Example applies only when READ commands are issued to same device.
Nonconsecutive read data is illustrated in Figure 20 on page 40. Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing, shown in Table 9 on page 41.
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to
complete the entire READ burst. However, a READ (with auto precharge disabled) using
BL = 8 operation may be interrupted and truncated only by another READ burst as long
as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. READ burst BL = 8 operations may not be interrupted or truncated with
any command except another READ command, as shown in Figure 21 on page 40.
COMMAND
COMMAND
COMMAND
DQS, DQS#
DQS, DQS#
ADDRESS
ADDRESS
ADDRESS
CK#
CK#
DQ
DQ
CK
CK
READ
Bank,
READ
Bank,
Col n
Col n
T0
T0
t
t
RL = 3
t
CCD
CCD
AC,
NOP
NOP
T1
T1
RL = 4
t
DQSCK, and
39
READ
Bank,
READ
Bank,
Col b
Col b
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
T2n
512Mb: x4, x8, x16 DDR2 SDRAM
T3
NOP
T3
NOP
DON’T CARE
DO
n
T3n
T3n
T4
T4
NOP
NOP
DO
n
TRANSITIONING DATA
T4n
T4n
©2004 Micron Technology, Inc. All rights reserved.
T5
T5
NOP
NOP
DO
b
T5n
T5n
T6
T6
NOP
NOP
READs
DO
b
T6n
T6n