MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 62

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 43:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
COMMAND 5
ADDRESS
DQS#,
ODT 8
CKE 1
DQS
CK#
CK 1
DM
DQ
Self Refresh
t AOFD / t AOFPD 8
NOP
t RP 2
T0
Notes:
t CH
Enter self refresh
mode (synchronous)
t CL
10. CKE must stay HIGH until
11. Once exiting SELF REFRESH, ODT must remain LOW until
1. Clock must be stable and meeting
2. Device must be in the all banks idle state prior to entering self refresh mode.
3.
4.
5. REF = REFRESH command.
6. Self refresh exit is asynchronous; however,
7. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which
8. ODT must be disabled and R
9. Once self refresh has been entered,
REF
T1
refresh mode and at least 1 x
t
t
clock edge where CKE HIGH satisfies
allows any non-READ command.
SELF REFRESH at state T1.
go back LOW after
XSNR is required before any non-READ command can be applied.
XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
t CK 1
T2
t CKE (MIN)
t
XSNR is satisfied.
Ta0
9
t
XSRD is met; however, if self refresh is being re-entered, CKE may
t CK 1
TT
62
t
CK prior to exiting self refresh mode.
off (
Exit self refresh
mode (asynchronous)
Ta1
t
t
CK specifications at least 1 x
AOFD and
t
CKE (MIN) must be satisfied prior to exiting self refresh.
t
ISXR.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t ISXR 6
NOP 7
t
XSNR and
Ta2
512Mb: x4, x8, x16 DDR2 SDRAM
t
AOFPD have been satisfied) prior to entering
t CKE 10
t XSNR 3, 6, 11
t
XSRD timing starts at the first rising
NOP 7
t
Tb0
XSRD is satisfied.
t XSRD 4,6
DON’T CARE
©2004 Micron Technology, Inc. All rights reserved.
t
CK after entering self
VALID 3
VALID
Tc0
Self Refresh
Indicates a break in
time scale
VALID 4
VALID 3
Td0
t IH
t IH