MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 66

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
CKE Truth Table
Notes 1–3, 12
Notes:
10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD
11. Minimum CKE HIGH time is
12. The state of ODT does not affect the states described in this table. The ODT function is not
13. Power-down modes do not perform any REFRESH operations. The duration of power-down
14. “X” means “Don’t Care” (including floating around V
1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previ-
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of com-
4. All states and sequences not shown are illegal or reserved unless explicitly described else-
5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occur-
6. Self refresh mode can only be entered from the all banks idle state.
7. Must be a legal command as defined in the Command Truth Table, Table 5 on page 29.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. Valid commands for self refresh exit are NOP and DESELECT only.
Bank(s) active
All banks idle
Power-down
Self refresh
ous clock edge.
mand (n).
where in this document.
ring during the
is satisfied.
MODE operations, or PRECHARGE operations are in progress. See “Power-Down Mode” on
page 64 and See “Self Refresh” on page 61 for a list of detailed restrictions.
requires a minimum of 3 clock cycles of registration.
available during self refresh. See “ODT Timing” on page 74 for more details and specific
restrictions.
mode is therefore limited by the refresh requirements.
However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled
via EMR(1).
Current
State
Previous
Cycle
(n-1)
t
XSNR period. READ commands may be issued only after
H
H
H
H
L
L
L
L
CKE
Cycle (n)
Current
t
CKE = 3 x
66
H
H
H
L
L
L
L
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP Precharge power-down
Command (n)
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS#, WE#
CS#, RAS#,
CK. Minimum CKE LOW time is
REFRESH
Shown in Table 5 on page 29
X
X
512Mb: x4, x8, x16 DDR2 SDRAM
REF
Maintain power-down
) in self refresh and power-down.
Maintain self refresh
Active power-down
Self refresh entry
Power-down exit
Self refresh exit
Action (n)
©2004 Micron Technology, Inc. All rights reserved.
entry
entry
Power-Down Mode
t
CKE = 3 x
t
XSRD (200 clocks)
4, 8, 10, 11
t
CK. This
4, 8, 10
6, 9, 11
Notes
13, 14
4, 5, 9
4, 8
14
7