MT48H16M32LFCM-75 IT:A TR Micron Technology Inc, MT48H16M32LFCM-75 IT:A TR Datasheet - Page 24

• Manufacturer Part Number: MT48H16M32LFCM-75 IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M32LFCM-75 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 95mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1329-2

Figure 11:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
READ Command
Notes:
A9, A11, A12
1. EN AP = enable auto precharge
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL -1.
Figure 7 on page 16 shows CLs of two and three; data element n + 3 is either the last of a
burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule associated with a prefetch archi-
tecture. A READ command can be initiated on any clock cycle following a previous
READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 12 on page 25, or each subsequent READ may be performed to a
different bank.
BA0, BA1
DIS AP = disable auto precharge
A0–A8
CAS#
A10
RAS#
WE#
CKE
CLK
CS#
1
HIGH
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
COLUMN
ADDRESS
ADDRESS
DIS AP
EN AP
BANK
24
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©2005 Micron Technology, Inc. All rights reserved.
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