MT48H16M32LFCM-75 IT:A TR Micron Technology Inc, MT48H16M32LFCM-75 IT:A TR Datasheet - Page 6

IC SDRAM 512MBIT 133MHZ 90VFBGA

MT48H16M32LFCM-75 IT:A TR

Manufacturer Part Number
MT48H16M32LFCM-75 IT:A TR
Description
IC SDRAM 512MBIT 133MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48H16M32LFCM-75 IT:A TR

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
8/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
95mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1329-2
Functional Block Diagrams
Figure 2:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
BA0, BA1
A0–A12,
CAS#
RAS#
WE#
CKE
CLK
CS#
15
32 Meg x 16 SDRAM
ADDRESS
REGISTER
MODE REGISTER
EXT MODE
REGISTER
CONTROL
LOGIC
13
The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
COUNTER
REFRESH
13
10
2
13
ADDRESS
2
ROW-
MUX
COUNTER/
CONTROL
COLUMN-
ADDRESS
LATCH
LOGIC
BANK
13
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
ADDRESS
DECODER
BANK0
LATCH
ROW-
AND
10
6
8,192
READ DATA LATCH
(8,192 x 1,024 x 16)
SENSE AMPLIFIERS
DQM MASK LOGIC
WRITE DRIVERS
I/O GATING
DECODER
COLUMN
MEMORY
BANK0
ARRAY
16,384
1,024
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(x16)
BANK1
BANK2
BANK3
BA1
0
0
1
1
Functional Block Diagrams
16
16
2
BA0
0
1
0
1
REGISTER
REGISTER
OUTPUT
©2005 Micron Technology, Inc. All rights reserved.
DATA
DATA
INPUT
Bank
0
1
2
3
2
16
DQML,
DQMH
DQ0–
DQ15

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