MT48H16M32LFCM-75 IT:A TR Micron Technology Inc, MT48H16M32LFCM-75 IT:A TR Datasheet - Page 40

• Manufacturer Part Number: MT48H16M32LFCM-75 IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M32LFCM-75 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 95mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1329-2

WRITE with Auto Precharge
Figure 33:
Figure 34:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
WRITE With Auto Precharge Interrupted by a READ
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
Internal
States
Internal
States
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is LOW.
COMMAND
COMMAND
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 33).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 34).
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
t
WR is met, where
Page Active
Page Active
T0
T0
NOP
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
t
WR begins when the WRITE to bank m is registered. The last
a + 1
a + 1
T2
T2
40
D
D
NOP
NOP
IN
IN
BANK m,
READ - AP
a + 2
T3
COL d
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
WR - BANK n
READ with Burst of 4
WR is met, where
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
CL = 3 (bank m)
d
t
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
t
WR begins when the READ to
T6
T6
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
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d
IN
Precharge
DON’T CARE
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
OUT
t RP - BANK m
IN
Write-Back
Operations