PCA9632DP1,118 NXP Semiconductors, PCA9632DP1,118 Datasheet
PCA9632DP1,118
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PCA9632DP1-T
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PCA9632DP1,118 Summary of contents
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PCA9632 4-bit Fm+ I Rev. 03 — 15 July 2008 1. General description The PCA9632 Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in upgrade for the PCA9633 with 40 power reduction. In Individual brightness control ...
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... NXP Semiconductors The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632 through the I their default state causing the outputs to be set high-impedance. This allows an easy and quick way to reconfigure all device registers to the same condition. 2. Features I 40 power reduction compared to PCA9633 I 4 LED drivers ...
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... NXP Semiconductors I 5.5 V tolerant inputs +85 C operation I ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: TSSOP8, TSSOP10, HVSON8, HVSON10 3. Applications I RGB or RGBA LED drivers for color mixing ...
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... NXP Semiconductors 5. Block diagram PCA9632 SCL INPUT FILTER SDA POWER- RESET V SS REGISTER X BRIGHTNESS CONTROL 6.25 kHz/ 1.56 kHz 400 kHz OSCILLATOR Fig 1. Block diagram of PCA9632 PCA9632_3 Product data sheet 10-pin version C-BUS CONTROL PWM 0.09 Hz GRPFREQ REGISTER 190 Hz Rev. 03 — 15 July 2008 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. terminal 1 index area Fig 4. 6.2 Pin description Table 2. Symbol LED0 LED1 LED2 LED3 V SS SCL SDA V DD [1] HVSON8 package die supply ground is connected to both the V V pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, ...
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... NXP Semiconductors Table 3. Symbol LED0 LED1 LED2 LED3 SCL SDA V DD [1] HVSON10 package die supply ground is connected to both the and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors • slave devices that are designed to respond to the General Call address (0000 000) • High-speed mode (Hs-mode) master code (0000 1XX) a. 8-pin version Fig 6. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. ...
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... NXP Semiconductors 7.1.4 Software reset I The address shown in performed by the master. The Software Reset address (SWRST Call) must be used with R R the PCA9632 does not acknowledge the SWRST. See “Software reset” Fig 7. Remark: The Software Reset regular I 7.2 Control register ...
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... NXP Semiconductors Table 4. AI2 Remark: Other combinations not shown in reserved and must not be used for proper device operation. AI[2:0] = 000 is used when the same register must be accessed several times during a single I is overwritten each time the register is accessed during a write operation. ...
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... NXP Semiconductors 7.3 Register definitions Table 5. Register summary Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be acknowledged. When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation. ...
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... NXP Semiconductors 7.3.1 Mode register 1, MODE1 Table 6. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access 7 AI2 read only 6 AI1 read only 5 AI0 read only 4 SLEEP R/W 3 SUB1 R/W 2 SUB2 R/W 1 SUB3 R/W 0 ALLCALL R/W [1] It takes 500 s max. for the oscillator and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window ...
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... NXP Semiconductors 7.3.3 PWM registers PWMx — Individual brightness control registers Table 8. Legend: * default value. Address 02h 03h 04h 05h While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99 ...
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... NXP Semiconductors 7.3.4 Group duty cycle control, GRPPWM Table 9. Legend: * default value. Address 06h When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘ ...
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... NXP Semiconductors 7.3.5 Group frequency, GRPFREQ Table 10. Legend: * default value. Address 07h GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to logic 1. Value in this register is a ‘don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). ...
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... NXP Semiconductors Once subaddresses have been programmed to their right values, SUBx bits need to be set order to have the device acknowledging these addresses (MODE1 register). Only the 7 MSBs representing the I register is a read-only bit (0). When SUBx is set to 1, the corresponding C-bus read or write sequence. ...
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... NXP Semiconductors 4. Once the SWRST Call address has been sent and acknowledged, the master sends 2 bytes with 2 specific values (SWRST data byte 1 and byte 2): a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to A5h, the PCA9632 does not acknowledge it. ...
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... NXP Semiconductors Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits LEDOUT INVRT OUTDRV Upper transistor LED driver off LED driver Individual 0 1 brightness control Individual + group 0 1 dimming/ blinking [1] External pull-up or LED current limiting resistor connects LEDn to V 7.7 Individual brightness control with group dimming/blinking A 1.5625 kHz fi ...
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... NXP Semiconductors brightness control signal (LEDn) Minimum pulse width for LEDn brightness control is 2.5 s. Fig 9. Individual LED brightness control signals brightness control signal (LEDn 2.5 s with 16) (GRPPWM Register) group dimming signal resulting brightness + group dimming signal Minimum pulse width for LEDn brightness control is 2.5 s. ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 13. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) 10-pin version only. (2) See Table 5 for register definition. Fig 15. Write to a specific register (1) slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave (1) 10-pin version only. Fig 16. Write to all registers using the Auto-Increment feature ...
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... NXP Semiconductors (1) slave address START condition R/W acknowledge from slave PWM2 register (cont.) A acknowledge from slave (1) 10-pin version only. Fig 17. Multiple writes to Individual brightness registers only using the Auto-Increment feature (1) slave address START condition R/W acknowledge from slave data from MODE2 register (cont ...
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... NXP Semiconductors slave address sequence ( START condition LED All Call I sequence ( START condition (1) 10-pin version is used for this figure. Four PCA9632DP2 or PCA9632TK2 and same sequence (A) (above) is sent to each of them. A[1: 11. (2) ALLCALL bit in MODE1 register is equal to logic 1 for this example. (3) OCH bit in MODE2 register is equal to logic 1 for this example. ...
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... NXP Semiconductors 10. Application design-in information C-BUS/SMBus MASTER Fig 21. Typical application Question 1: What kind of edge rate control is there on the outputs? • The typical edge rates depend on the output configuration, supply voltage, and the applied load. The outputs can be configured as either open-drain NMOS or totem pole outputs ...
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... NXP Semiconductors Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot. Why? • The IC outputs can be set to either open-drain or push-pull and default to push-pull outputs. In this application with the Zener diodes, they need to be set to open-drain since in the push-pull architecture there is a low resistance path to ground through the Zener and this is causing the IC to overheat ...
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... NXP Semiconductors 12. Static characteristics Table 18. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current leakage current ...
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... NXP Semiconductors 13. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a BUF STOP and START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated SU;STA START condition t set-up time for STOP SU;STO condition ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 22. Definition of timing START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 23. I C-bus timing diagram 14. Test information Fig 24. Test circuitry for switching times PCA9632_3 Product data sheet ...
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... NXP Semiconductors 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0 0.2 0.00 0.2 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP10: plastic thin shrink small outline package; 10 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 22. Acronym CDM DUT ESD HBM 2 I C-bus LCD LED LSB MM MSB NMOS ...
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... NXP Semiconductors 19. Revision history Table 23. Revision history Document ID Release date PCA9632_3 20080715 • Modifications: Section 7.1.1 “Regular I • Table 5 “Register • Figure 20 “Software Reset (SWRST) Call – changed “Byte 1 = 0xA5” to “Byte 1 = A5h” – changed “Byte 2 = 0x5A” to “Byte 2 = 5Ah” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 6 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 6 2 7.1.2 LED All Call I C-bus address . . . . . . . . . . . . . . ...