NCP1650DR2 ON Semiconductor, NCP1650DR2 Datasheet - Page 30

• Manufacturer Part Number: NCP1650DR2
• Description: IC CTRLR PWR FACTOR PWM 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1650DR2

• Mode: Continuous Conduction (CCM), Discontinuous Conduction (DCM)
• Frequency - Switching: 100kHz
• Voltage - Supply: 10 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Switching Frequency: 25 KHz to 250 KHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Startup: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1650DR2OSTR

Power Amplifier
similar to the network for the voltage error amplifier. The
series RC on pin 8 will create a pole- -zero pair based on the
equations given.
Calculating the Loop Gain
conditions. At lower lines the bandwidth will decrease.
multiplier pole. Make sure that they are converted to dB’s.
Begin with all stages except the power amplifier, and
determine what the gain of the power amplifier needs to be
at the unity gain frequency. This loop is normally slower
than the voltage loop and will generally be a factor of 5 to 10
lower in bandwidth.
following plot:
--10
--20
--30
--40
The compensation for this amplifier will be determined
The power loop gain should be calculated using high line
Similar to the voltage loop, calculate the gains and power
The loop gain without the amplifier should resemble the
30
20
10
0
0.01
Figure 46. Power Loop without Power Amp
0.1
FREQUENCY (Hz)
1
10
POWER LOOP
POWER AMP
GAIN LESS
100
http://onsemi.com
1000
30
1.0 Hz, the power amplifier needs a gain of –27 dB
(0.045 v/v) at 1.0 Hz, with a zero at 0.7 Hz. The zero
frequency is chosen to match the pole frequency. Although
it is not essential to do this, it is a safe method of assuring a
stable system.
the zero frequency, the gain of the amplifier is:
a 470 Ohm resistor would be a good choice, and for a zero
at 0.7 Hz:
and a 470 mF cap would be a good choice. Using these two
values, the resulting open loop plot would be:
require adjustment in actual circuit conditions.
--20
--40
--60
--80
For this example it can be seen that for a bandwidth of
Since the frequency that we are interested in is greater than
As stated previously, these are calculated values, and may
60
40
20
0
or, R 8 = A v ∕G m = 0.045∕.0001 = 446 Ohms
0.01
Figure 47. Power Circuit Open Loop Gain
C 8 =
0.1
2 ⋅ π ⋅ 470 Ω ⋅ 0.7 Hz
A v = G m R 8
FREQUENCY (Hz)
1
1
10
= 483 mF
100
1000