L6740LTR STMicroelectronics, L6740LTR Datasheet

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Hybrid controller (4+1) for AMD SVID and PVID processors Features ■ Hybrid controller: compatible with PVI and SVI CPUs ■ Dual controller scalable phases for CPU CORE, 1 phase for NB ■ Dual-edge asynchronous architecture with tm ...

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Contents Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . . ...

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L6740L 6.8 NB section - maximum duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 On-the-fly VID transitions . . . . ...

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Typical application circuit and block diagram 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical 4+1 application circuit 2 1 PWRGOOD 41 PWROK VID0 35 PVI / SVID Bus VID1 36 VID2/SVD 40 ...

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L6740L Figure 2. Typical 3+1 application circuit 2 1 PWRGOOD 41 PWROK VID0 35 PVI / SVID Bus VID1 36 VID2/SVD 40 VID3/SVC 39 VID4 25 VID5 26 R OVP OVP / V_FIX 10 R OSC OSC ...

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Typical application circuit and block diagram Figure 3. Typical 2+1 application circuit 2 1 PWRGOOD 41 PWROK VID0 35 PVI / SVID Bus VID1 36 VID2/SVD 40 VID3/SVC 39 VID4 25 VID5 26 R OVP OVP / ...

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L6740L 1.2 Block diagram Figure 4. Block diagram CS1+ AMD SVI / PVI FLEXIBLE CS1- CS2+ CS2- CS3+ CS3- CURRENT BALANCE CS4+ CS4- PWM1 Σ PWM1 PWM2 Σ PWM2 PWM3 Σ PWM3 PWM4 Σ PWM4 OSC OSC 1.24V VCC VCC ...

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Pins description and connection diagrams 2 Pins description and connection diagrams Figure 5. Pins connection (top view) 2.1 Pin descriptions Table 2. Pin description Pin# Name 1 2 SGND 3 COMP 4 5 DROOP 6 VSEN 8/ ...

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L6740L Table 2. Pin description (continued) Pin# Name OVP / V_FIX 11 LTB_GAIN 12 PSI_L Pins description and connection diagrams Remote ground sense. FBG Connect to the negative side of ...

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Pins description and connection diagrams Table 2. Pin description (continued) Pin# Name OC_PHASE 22 23 NB_ISEN 24 25, VID4, VID5 26 27 OSC / FLT OC_AVG / 28 29 NB_OS 30 NB_FBG 10/44 Channel 4 current sense ...

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L6740L Table 2. Pin description (continued) Pin# Name 31 NB_VSEN 32 NB_DROOP 33 NB_FB 34 NB_COMP 35, VID0, VID1 36 37 PWROK 38 39 SVC / VID3 40 SVD / VID2 41 PWRGOOD Pins description and connection diagrams NB output ...

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Pins description and connection diagrams Table 2. Pin description (continued) Pin# Name 42 NB_ENDRV 43 ENDRV 44 NB_PWM 45 to PWM1 to 48 PWM4 Thermal pad 2.2 Thermal data Table 3. Thermal data Symbol Thermal resistance junction to ambient R ...

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L6740L 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V to PGND CC All other pins to PGNDx 3.2 Electrical characteristics Table 5. Electrical characteristics ( ± 15 Symbol Parameter ...

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Electrical specifications Table 5. Electrical characteristics (continued ± 15 Symbol Parameter PSI_L Voltage low Voltage positioning (CORE and NB section) CORE Output voltage accuracy NB OFFSET bias voltage OS, NB_OS OFFSET current range OFFSET ...

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L6740L 4 Device description and operation L6740L is a hybrid CPU power supply controller compatible with both parallel (PVI) and Serial (SVI) protocols for AMD K8 - second generation processors. The device provides complete control logic and protections for a ...

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Hybrid CPU support and CPU_TYPE detection 5 Hybrid CPU support and CPU_TYPE detection L6740L is able to detect the type of the CPU-core connected and to configure itself accordingly. At system start-up, on the rising-edge of the EN signal, the ...

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L6740L Table 6. Voltage identifications (VID) codes for PVI mode VID5 VID4 VID3 VID2 VID1 VID0 ...

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Hybrid CPU support and CPU_TYPE detection 5.3 SVI - serial interface SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave (L6740L). The master initiates and terminates SVI transactions and drives the ...

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L6740L transition for the addressed section(s) or, more in general, react to the sent command accordingly. Refer to L6740L is able to manage individual power OFF for both the sections. The CPU may issue a serial VID command to power ...

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Hybrid CPU support and CPU_TYPE detection Table 9. Data phase - serial VID codes Output SVI [6:0] voltage 000_0000 1.5500 000_0001 1.5375 000_0010 1.5250 000_0011 1.5125 000_0100 1.5000 000_0101 1.4875 000_0110 1.4750 000_0111 1.4625 000_1000 1.4500 000_1001 1.4375 000_1010 1.4250 ...

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L6740L 5.4.2 PWROK de-assertion Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored Pre-PWROK Metal VID and regulates all the planes to that level performing an On-the-Fly transition to that level. PWRGOOD is treated appropriately being ...

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Hybrid CPU support and CPU_TYPE detection Table 10. PSI strategy PSI_L GND Pull-Up to <3V Pull-Up to 3.3V Figure 8. System efficiency enhancement by PSI 5.4.4 HiZ management L6740L is able to manage HiZ through both the PWMx and driver ...

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L6740L 6 Output voltage positioning Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI and V_FIX) and by programming the droop function and offset to the reference of both the sections (See Figure monitoring the voltage drop ...

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Output voltage positioning 6.1 CORE section - phase # programming CORE section implements a flexible interleaved-phase converter. To program the desired number of phase, simply short to SGND the PWMx signal that is not required to be ...

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L6740L Figure 10. Current reading - CORE section (left) and NB section (right CSx- INFOx VDD Inductor DCR Current Sense The current read through the CSx+ / CSx- pairs is converted into a current I tional to the ...

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Output voltage positioning this case, simply connect a resistor R be proportional to the delivered current according to the following relationship: DCR ⋅ ------------ - DROOP case no additional information about the delivered ...

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L6740L 6.6 NB section - load-line and load-indicator (optional) This method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a depen- ...

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Output voltage positioning 1.240V ------------------- - OS_NB V OS_NB Caution: Offset implementation is optional, in case it is not desired, simply short the pin to SGND. Note: In the above formulas, R between NB_FB pin and the ...

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L6740L re-starts monitoring VID after the transition has finished on the next rising-edge available. OTFVID-clock frequency (F If the new VID code is more than 1 LSB different from the previous, the device will execute the transition stepping the reference ...

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Output voltage positioning 6.10 Soft-start L6740L implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. In SVI mode, soft-start time is intended as the time required by the ...

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L6740L 7 Output voltage monitoring and protections L6740L monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in order to manage OV, UV and PWRGOOD. The device shows different thresholds when in different operative conditions but the ...

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Output voltage monitoring and protections – Permanently sets the PWM of the non-involved section to HiZ while keeping ENDRV of the non-involved section low in order to realize an HiZ condition of the non-involved section. – Drives the OSC/ FLT ...

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L6740L Figure 13. FB disconnection protection FBG DISCONNECTED CORE_REFERENCE FB COMP CORE SECTION - VSEN AND FBG DISCONNECTION 7.3 PWRGOOD open-drain signal set free after the soft-start sequence has finished; it ...

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Output voltage monitoring and protections Typical design considers the intervention of the Average OC before the per-phase OC, leav- ing this last one as an extreme-protection in case of hardware failures in the external com- ponents. Typical design flow is ...

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L6740L rent operation since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the I dition is when the ON time reaches its maximum value (see ...

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Main oscillator 8 Main oscillator The controller embeds a dual-oscillator: one section is used for the CORE and multi phase programmable oscillator managing equal phase-shift among all phases and the other section is used for the NB ...

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L6740L 9 System control loop compensation The device embeds two separate and independent control loops for CORE and NB section. The control loop for NB section is a simple voltage-mode control loop with (optional) voltage positioning featured when DROOP pin ...

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System control loop compensation Figure 17. Control loop bode diagram and fine tuning (not in scale LOOP K R [dB] F ω ω ω To obtain the desired shape an R implementation. A zero at ...

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L6740L 10 LTB Technology™ LTB Technology™ further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load. By properly designing the ...

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LTB Technology™ ● Gain design. Through the LTBGAIN pin it is possible to modify the slope of the LTB Ramp in order to modulate the entity of the LTB response once the LT has been detected. In fact, the response ...

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L6740L 11 Layout guidelines Layout is one of the most important things to consider when designing high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper ...

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TQFP48 mechanical data and package dimensions 12 TQFP48 mechanical data and package dimensions Figure 19. TQFP48 mechanical data and package dimensions mm DIM. MIN. TYP 0.05 A2 0.95 1.00 b 0.17 0.22 c 0.09 D 8.80 9.00 D1 ...

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L6740L 13 Revision history Table 13. Document revision history Date 07-Jun-2007 01-Aug-2007 22-Sep-2008 Revision 1 First release 2 Databrief updated to datasheet 3 Updated coverpage Revision history Changes 43/44 ...

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