L6740LTR STMicroelectronics, L6740LTR Datasheet - Page 31

• Manufacturer Part Number: L6740LTR
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740LTR

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6298-2

L6740L
7
7.1
Output voltage monitoring and protections
L6740L monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in
order to manage OV, UV and PWRGOOD. The device shows different thresholds when in
different operative conditions but the behavior in response to a protection event is still the
same as described below.
Protections are active also during soft-start (See
ing OTF-VID transitions with an additional delay to avoid false triggering.
Table 12.
Programmable overvoltage
Once VCC crosses the turn-ON threshold and the device is enabled (EN = 1), L6740L pro-
vides an overvoltage protection for both the sections: when the voltage sensed by VSEN
and/or NB_VSEN overcomes the OV threshold, the controller:
Over-current (OC)
VSEN, NB_VSEN
Disconnection
Disconnection
FBG, NB_FBG
Under voltage
On-the-fly VID
Overvoltage
PWRGOOD
Protection
–
(OV)
(UV)
Permanently sets the PWM of the involved section to zero keeping ENDRV of that
section high in order to keep all the low-side MOSFETs on to protect the load of
the section in OV condition.
L6740L protection at a glance
SVI / PVI: Programmable threshold according to OVP pin.
V_FIX: Fixed to 1.8 V; OVP pin is externally shorted to SGND.
Action: PWMx = 0 and ENDRVx = 1; Other section (SVI only): PWMx = HiZ;
ENDRVx = 0; FLT driven High.
VSEN, NB_VSEN = VID -400 mV. Active after Ref > 500 mV
Action: All PWMx = HiZ; ENDRVx = 0; FLT driven high.
PWRGOOD is the logic AND between internal CORE and NB PGOOD in SVI
mode while is the CORE section PGOOD in PVI mode.
Each PGOOD is set to zero when the related voltage falls below the
programmed reference -250mV.
Action: section(s) continue switching, PWRGOOD driven low.
Set when VSEN > CS1- +600 mV.
Action: UV-Like
Internal comparator across the opamp to recover from GND losses.
Action: UV-like
Current monitor across inductor DCR.
Dual protection, per-phase and average.
Action: UV-like
Masked with the exception of OC with additional 16 clock delay to prevent from
false triggering (both SVI and PVI).
CORE
Output voltage monitoring and protections
Section
Section
6.10) while they are masked dur-
30 μA pull-up from NB_VSEN to set
OV (SVI Only).
Action: OV-Like
Current monitor across LS R
constant current, valley CLimit.
Action: UV-Like
NORTH BRIDGE
DS(on
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)
.