ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet
ISL8120IRZ-T
Specifications of ISL8120IRZ-T
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ISL8120IRZ-T Summary of contents
Page 1
... DDR tracking applications (VDDQ and VTT outputs). The output voltage of a ISL8120IRZEC-based converter can be precisely regulated to as low as the internal reference voltage 0.6V, with a system accuracy of ±0.9% over industrial temperature and line load variations. Channel 2 can track an external ramp signal for DDR/tracking applications ...
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... ISL8120IRZEC Ordering Information NUMBER ISL8120IRZEC ISL8120IRZ-TEC* ISL8120 IRZ *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Block Diagram (1/2) REFERENCE V = 0.6V REF VCC 700mV FB1 COMP1 VSEN1+ VSEN1- UNITY GAIN DIFF AMP1 VMON1 EN/FF1 PVCC VCC POWER-ON RESET (POR) OTP OVER-TEMPERATURE PROTECTION (OTP) CHANNEL 1 SOFT-START AND FAULT LOGIC V SAW1 REF AVG_OCP + ...
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Block Diagram (2/2) RELATIVE PHASE CONTROL k*VDDQ V REF VCC 700mV FB2 COMP2 V REF VSEN2+ VSEN2- UNITY GAIN DIFF AMP2 VMON2 CLKOUT/REFIN EN/FF2 OTP POR MASTER CLOCK OSCILLATOR GENERATOR CHANNEL 2 SOFT-START AND FAULT LOGIC V REF2 SAW2 M/D ...
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... Typical Application I (Dual Regulators with DCR Sensing and Remote Sense) VIN +3.3 TO +22V C F2 VIN C F3 ISL8120IRZEC CLKOUT/REFIN VCC PGOOD R FS FSYNC EN2/FF2 EN1/FF1 R SET ISET ISHARE 5 ISL8120IRZEC VIN_F HFIN C F1 VCC PVCC BOOT1 UGATE1 Q1 PHASE1 LGATE1 Ω ISEN1A ISEN1B COMP1 ...
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... Note 1: Set the upper resistor little higher than R*(VDDQ/0 will set the final REFIN voltage (stead state voltage after soft-start) derived from the VDDQ little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start. Note 2: Another way to set REFIN voltage is to connect VMON1 directly to REFIN pin. 6 ISL8120IRZEC VIN_F L IN ...
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... FSYNC CLKOUT/REFIN FB2 GND VSEN2+ 7 ISL8120IRZEC DS(ON VCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B COMP1/2 Z ISL8120IRZEC COMP1 FB1 VMON1/2 VSEN1+ VSEN1- VIN_F BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A R ISEN2B VCC VSEN2- GND Sensing and Voltage Trimming) C HFIN C BIN C BOOT1 Q1 L OUT1 ...
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... FB2 ISHARE VMON2 VSEN2+ ISET VSEN2- R PVCC VCC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS EN/FF1,2 LGATE1 PGOOD ISL8120IRZEC EN/FF1,2 ISEN1A PHASE 1 AND 3 BOOT2 ISEN1B UGATE2 COMP1/2 PHASE2 FB1 VMON1/2 LGATE2 VSEN1+ ISEN2A VSEN1- ISEN2B ISHARE FB2 VSEN2+ VSEN2- CLKOUT/REFIN ISET GND ...
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... ISL8120IRZEC ISEN1A PHASE 2 AND 4 ISEN1B FB2 COMP1/2 FB1 VMON1/2 ISET R GND FSYNC ISHARE R PVCC VCC CC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 ISL8120IRZEC ISEN1A ISEN1B PHASE 1 AND 3 COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1- ISHARE FB2 CLKOUT/REFIN ISET GND R VIN_F BOOT2 Q1 L OUT2 ...
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... ISHARE VMON2 VSEN2+ GND PHASE 2 VSEN2- R PVCC VCC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 PGOOD EN/FF1, 2 ISEN1A ISL8120IRZEC BOOT2 ISEN1B UGATE2 Q3 COMP1/2 PHASE2 FB1 VMON1/2 LGATE2 Q4 VSEN1+ ISEN2A VSEN1- ISEN2B ISHARE FB2 VCC VSEN2+ PHASE 1 AND 3 CLKOUT/REFIN VSEN2- VCC ISET ...
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... VCC CLKOUT/REFIN FSYNC ISHARE FB2 PHASE 2 AND 5 ISET GND R R VCC PVCC BOOT1 VIN UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 COMP1/2 ISL8120IRZEC VMON2 R OS1 VSEN1+ VSEN1- ISHARE FB2 CLKOUT/REFIN PHASE 1 AND 4 ISET GND R VIN_F BOOT3 Q1 L OUT3 Q2 R ISEN3 R VIN_F ...
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... VSEN1+ VSEN1- 2-PHASE FSYNC MODULE #1 FB2 ISHARE GND ISET R R PVCC VCC CC1 BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 ISEN1A ISEN1B COMP1/2 FB1 ISL8120IRZEC VMON1/2 VSEN1+ VSEN1- ISHARE 2-PHASE MODULE #2 FB2 CLKOUT/REFIN GND ISET R VIN_F BOOT3 Q5 L OUT3 C Q6 OUT2 R ...
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... VMON1/2 (PHASE 2 AND 5) VSEN1+ VSEN1- CLKOUT/REFIN FSYNC ISHARE/ISET FB2 GND OUTPUT 2 R VCC PVCC BOOT1 VIN UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 ISL8120IRZEC COMP1/2 (PHASE 1 AND 4) VMON2 R OS1 VSEN1+ VSEN1- ISHARE/ISET FB2 OUTPUT 1 CLKOUT/REFIN GND VIN_F BOOT3 Q1 L OUT3 V OUT3 Q2 C ...
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... System Soft-Start Delay (Note 3) ENABLE Turn-On Threshold Voltage Hysteresis Sink Current Undervoltage Lockout Hysteresis (Note 3) Sink Current Sink Impedance 14 ISL8120IRZEC Thermal Information Thermal Resistance (Typical Notes QFN Package . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150° 0.3V Pb-free Reflow Profile ...
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... Unity Gain Bandwidth (Note 3) Negative Input Source Current (Note 3) Maximum Source Current for Current Sharing (Typical Application VIII) (Note 3) Input Impedance Output Voltage Swing (Note 3) Input Common Mode Range (Note 3) 15 ISL8120IRZEC SYMBOL TEST CONDITIONS R = 100k, Figure 20 FS VCC = 5V; -40°C < T <+85°C A Δ ...
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... PGOOD Low Output Voltage Sinking Impedance Maximum Sinking Current (Note 3) OVERVOLTAGE PROTECTION OV Latching Up Trip Point OV Non-Latching Up Trip Point (Note 3) LGATE Release Trip Point OVER-TEMPERATURE PROTECTION Over-Temperature Trip (Note 3) Over-Temperature Release Threshold (Note 3) 16 ISL8120IRZEC SYMBOL TEST CONDITIONS Tri-State VSEN- MON1,2 R 45mA Source Current UGATE R ...
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... ISL8120IRZEC will lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the CLKOUT input signal from another ISL8120IRZEC or an external clock. The internal oscillator synchronizes with the leading edge of the input signal. EN/FF1, 2 (Pins 4, 6) These are triple function pins. The input voltages to these pins are compared with a precision 0 ...
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... Channel 2’s internal reference through this pin for DDR/tracking applications (see “Internal Reference and System Accuracy” on page 31). 2. The ISL8120IRZEC operates as a dual-PWM controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on REFIN (see “DDR and Dual Mode Operation” on page 30) ...
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... PWM) to synchronize with another ISL8120IRZEC, which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output converter can be constructed with two ISL8120IRZECs operating in Mode (Mode 7A). If the share bus is not connected between ICs, each IC could generate an independent output (Mode 7B). When the ...
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... NOTE: “2ND CHANNEL WRT 1ST” is referred to as “channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells”. For example, 90° with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90°; -60° with 2ND CHANNEL WRT 1ST means channel 2 leads channel 1 by 60°. 20 ISL8120IRZEC TABLE 1. ISHARE (I/O) REPRESENTS ...
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... IC) 120° ND CH1 UG (2 IC) ND CH2 UG(2 IC, OFF, EN2/FF2 = 0) VCC VSEN2- VSEN2+ 700mV DIFF AMP2 FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL 21 ISL8120IRZEC 1-D 180° D 90° D 180° D 4-PHASE TIMING DIAGRAM (MODE 7A) 1-D 240° D 120° 1-D D 3-PHASE TIMING DIAGRAM (MODE 6) ...
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... Functional Description Initialization Initially, the ISL8120IRZEC Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is pulled to be above 0.8V, all input supplies exceed their POR thresholds and the PLL locking time expires, as shown in Figure 4 ...
Page 23
... The ISL8120IRZEC has the ability to work under a pre-charged output (see Figure 8). The output voltage would not be yanked down during pre-charged start-up. If the pre- charged output voltage is greater than the final target level but prior to 113% setpoint, the switching will not start until the output voltage reduces to the target voltage and the first PWM pulse is generated (see Figure 9) ...
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... OV event with the corresponding VMON as the monitor. In multiphase mode, both channels respond simultaneously when either triggers an OV event. 24 ISL8120IRZEC To protect the overall power trains in case of only one channel of a multiphase system detecting OV, the low-side MOSFET always turns on at the conditions of EN/FF = LOW ...
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... Current Loop When the ISL8120IRZEC operates in 2-phase mode, the current control loop keeps the channel’s current in balance. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the voltage developed across the DCR of the inductor, r DS(ON) MOSFETs precision resistor, is filtered and sampled for 175ns ...
Page 26
... ISHARE and ISET pins source a copy of I offset, for example, the full-scale will be 120µA. If one single external resistor is used as R ISHARE bus to ground for all the ICs in parallel, R should be set equal to R number of the ISL8120IRZEC controllers in parallel or multiphase operations), and the share bus voltage . The CS1 (V ISHARE current of all active channels ...
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... VSEN- pulled to VCC, as shown in Figure 15. Current Share Control Loop in Multi-Module with Independent Voltage Loop The power module controlled by ISL8120IRZEC with its own voltage loop can be paralleled to supply one common output load with its integrated Master-Slave current sharing control, as shown in “Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)” ...
Page 28
... When VIN drops below 5.0V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear regulator. When used with an external 5V supply, VIN pin is recommended to be tied directly to PVCC. 28 ISL8120IRZEC 2.65V TO 5.6V 2Ω 1µF PVCC VCC ...
Page 29
... connecting the FSYNC pin to an external square pulse GD waveform (such as the CLOCK signal, typically 50% duty C DS cycle from another ISL8120IRZEC), the ISL8120IRZEC will GI1 synchronize its switching frequency to the fundamental C frequency of the input waveform. The maximum voltage FSYNC pin is VCC + 0 ...
Page 30
... As some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high impedance by pulling VSEN- within 700mV of VCC. In such an event, the VMON pin can be 30 ISL8120IRZEC VOUT ...
Page 31
... In DDR mode, Channel 1 delays 60° over Channel 2. In Dual mode, depending upon the resistor divider level of REFIN from VCC, the ISL8120IRZEC operates as a dual PWM controller for two independent regulators with a phase shift as shown in Table 2. The phase shift is latched as VCC raises above POR and cannot be changed on-the-fly ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 ISL8120IRZEC ⋅ ⎛ ...
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... Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 33 ISL8120IRZEC ± 0.1 ( 28X (32X 32X 0 . 60) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ...