ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 26

• Manufacturer Part Number: ISL8120IRZ-T
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The signal I
channel’s scaled current (I
correction signal for each channel. The current correction
signal keeps each channel’s output current contribution
balanced relative to the other active channel.
For multiphase operation, the share bus (V
represents the average current of all active channels and
compares with each IC’s average current (I
I
by V
for each individual channel. Each current correction signal is
then subtracted from the error amplifier output and fed to the
individual channel PWM circuits.
When both channels operate independently, the average
function is disabled and generates zero average current
(I
disabled. The I
channel 1 makes any necessary current correction by
comparing its channel current (represented by V
the share bus (V
connect to other ICs, the ISET and ISHARE pins can be
shorted together and grounded via a single resistor to
ensure zero share error.
Note that the common mode input voltage range of the
current sense amplifiers is VCC - 1.8V. Therefore, the
r
voltage greater than VCC - 1.8V. For example, application of
3.3V output is suggested to use r
In addition, the R-C network components (for DCR sensing)
are selected such that the RC time constant matches the
inductor L/DCR time constant. Otherwise, it could cause
undershoot/overshoot during load transient and start-up. C is
AVG
DS(ON)
SHARE BUS
AVG
R
ISHARE
ISET
or I
R
= 0), and current correction block of Channel 2 is also
ISET
CS1
sensing should be used for applications with output
) to generate current share error signal (I
AVG
depending upon the configuration, represented
AVG_CS
is then subtracted from the individual
ISHARE
ISHARE
ISET
R
FIGURE 14. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION
ISHARE
is the Channel 1 current I
). When the share bus does not
CURRENT
MIRROR
BLOCK
CS1
26
= R
or I
ISET
DS(ON)
CS2
/N
I
AVG_CS
CTRL
) to produce a current
sensing.
AVG_CS
ISHARE
ERROR
AMP 1
I
CS1
-
ISET
CS1
CS_ERR
-
)
equals to
CURRENT
I
I
I
MIRROR
AVG
DROOP
AVG_CS
∑
BLOCK
. The
) with
I
ISL8120IRZEC
CSH_ERR
+
= (I
)
+ 15µA = I
-
CS1
= I
AVG
+ I
∑
CS2
+
or I
AVG_CS
) / 2
CS1
V
I
ERROR1
CSH_ERR
typically set to 0.1µF or higher, while R is calculated with
Equation 5.
Figure 13 shows a simple and flexible configuration for both
r
Current Share Control in Multiphase Single Output
The I
2-phase mode) or only Channel 1 (I
ISHARE and ISET pins source a copy of I
offset, for example, the full-scale will be 120µA. If one single
external resistor is used as R
ISHARE bus to ground for all the ICs in parallel, R
should be set equal to R
number of the ISL8120IRZEC controllers in parallel or
multiphase operations), and the share bus voltage
(V
current of all active channels. Another way to set R
to put one resistor in each IC’s ISHARE pin and use the
same value with R
the total equivalent resistance value is also R
The voltage (V
current of the corresponding device and compared with the
share bus (V
(I
adjust each channel’s PWM pulse accordingly.
The current share function provides at least 10% overall
accuracy between ICs, 5% within the IC when using a 1%
resistor to sense a 10mV signal. The current share bus
works for up to 12-phase.
For multiphase implementation, one single error amplifier
should be used for the voltage loop. Therefore, all other
R
DS(ON)
CSH_ERR
ISHARE
=
+ 15µA = ISET = ISHARE
----------------------- -
C DCR
AVG_CS
I
AVG_CS
•
I
CS2
L
and DCR sensing.
) set by the R
ERROR
AMP 2
) is then fed into the current correction block to
ISHARE
is the average current of both channels (I
-
ISET
-
∑
ISET
) set by R
). The current share error signal
+
ISHARE
(R
ISET
ISHARE =
-
/N
ISET
ISHARE
+
CTRL
represents the average
∑
represents the average
CS1,
R
V
(where N
connecting the
ISET
ERROR2
700mV
any other modes).
AVG_CS
), in which case
VCC
VSEN2-
ISET
CNTL
/N
with 15µA
ISHARE
April 21, 2009
ISHARE
CTRL
is the
FN6763.1
(EQ. 5)
AVG,
.
is