ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 27

• Manufacturer Part Number: ISL8120IRZ-T
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

channels’ error amplifiers should be disabled with their
corresponding VSEN- pulled to VCC, as shown in Figure 15.
Current Share Control Loop in Multi-Module with
Independent Voltage Loop
The power module controlled by ISL8120IRZEC with its own
voltage loop can be paralleled to supply one common output
load with its integrated Master-Slave current sharing control,
as shown in “Typical Application VIII (Multiple Power
Modules in Parallel with Current Sharing Control)” on
page 12. A resistor R
VSEN1- pin and the lower resistor of the voltage sense
resistor divider for each module. With this resistor, the
correction current sourcing from VSEN1- pin will create a
voltage offset to maintain even current sharing among
modules. The recommended value for the VSEN1- resistor
R
unity gain amplifier input pin impedance compatibility. The
maximum source current from VSEN1- pin is 350µA, which
is combined with R
regulation range. The generated correction voltage on R
is suggested to be within 5% of VREF (0.6V) to avoid fault
trigging of UV/OV and PGOOD during dynamic events.
To attain good current balance in system start up preventing
single module from overcurrent, the paralleled modules are
recommended to be synchronized and the enable pins (EN/FF)
should be tied together to initial start-up at the same instant.
Overcurrent Protection
The OCP function is enabled at start-up. When both
channels operate independently, the average function is
disabled and generates zero average current (I
Channel 2 current (I
and has its own independent overcurrent protection; while
the 7 clock cycles delay is bypassed. The Channel 1’s
current (I
with an external resistor R
CSR
is 100Ω and it should not be large in order to keep the
R
ISET1
CS1
) plus 15µA offset forms a voltage (V
CSR
CS2
CSR
ISET
VSEN1/2- COM1/2
ISL8120IRZEC
to determine the current sharing
) is compared with I
ISHARE
needs to be inserted between
ISHARE
27
R
FIGURE 15. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION
ISHARE1
and compares with a
1
SHARE BUS
TRIP
R
ISET2
AVG
(105µA)
ISHARE
= 0). The
ISL8120IRZEC
CSR
ISET
R
VSEN2-
)
ISHARE_
ISL8120IRZEC
ISHARE
VCC
R
COM1/2
= R
ISHARE2
ISET_
precision 1.2V threshold (±1%, 50mV hysteresis); while the
105µA OCP comparator with 7-cycle delay is also activated.
In multiphase operation, the V
average current of all active channels and compares with a
precision 1.2V threshold (±1%, 50mV hysteresis) to
determine the overcurrent condition, while each channel has
additional overcurrent trip point at 105µA with 7-cycle delay.
This scheme helps protect against loss of channel(s) in
multi-phase mode so that no single channel could carry
more than 105µA in such event. See Figure 13. Note that it
is not necessary for the R
same level as the 105µA OCP comparator if the application
allows. For instance, when Channel 1 operates
independently, the OC trip set by 1.2V comparator can be
lower than 105µA trip point as shown in Equation 6.
where N is the number of phases; NCNTL is the number of
the ISL8120IRZEC controllers in parallel or multiphase
operations; I
point; t
350ns; R
equivalent resistance in ISHARE pin bus of all ICs in
multiphase or module parallel operation.
The overcurrent trip current source is trimmed to 105µA
±10% for both channels, while the overcurrent threshold
(represented by V
Channel 1 depending upon configuration) is a precision 1.2V
±1% with 50mV hysteresis.
For the R
usually higher than the number calculated from Equation 6.
R
R
2
ISHARE
ISEN1
VSEN1-
VSEN1+
MIN_OFF
=
ISHARE
ISEN
=
⎛
⎜
⎝
--------------------------------------------------------------------------------------------------------------------- -
I
--------- -
-------------- -
I
TRIP
OC
N
TRIP
1V
chosen for OCP setting, the final value is
+
is the minimum Ugate turn off time that is
in Equation 6 represents the total
V
--------------- -
= 105µA; IOC is the load overcurrent trip
ISHARE
OUT
L
ISET
•
VSEN1/2- COM1/2
R
⎛
⎝
ISL8120IRZEC
) for multiphase operation (or
ISHARE
ISET
--------------- - t
2F
1 D
ISHARE
–
I
SW
TRIP
ISHARE
=
R
–
ISHARE3
R
to be scaled to trip at the
MIN_OFF
ISHARE
3
represents the
⎞
⎠
⋅
⎞
⎟
⎠
N
•
CNTL
DCR
R
ISET3
April 21, 2009
(EQ. 6)
FN6763.1