ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 31

• Manufacturer Part Number: ISL8120IRZ-T
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

loading, Channel 1 might drop faster than Channel 2. To solve
this race condition, Channel 2 can either power up from
Channel 1 or bridge the Channel 1 with a high current
Schottky diode. If the system requires to shutdown both
channels when either has a fault, tying EN/FF1 and EN/FF2
will do the job. In DDR mode, Channel 1 delays 60° over
Channel 2.
In Dual mode, depending upon the resistor divider level of
REFIN from VCC, the ISL8120IRZEC operates as a dual
PWM controller for two independent regulators with a phase
shift as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on-the-fly.
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of 0.9% over industrial temperature range.
While the remote sense is not used, its offset (V
should be included in the tolerance calculation. Equations 9
and 10 show the worst case of system accuracy calculation.
MODE
DDR
Dual
Dual
Dual
REFIN RANGE
29% to 45% of
45% to 62% of
<29% of VCC
62% to VCC
DECODING
VOUT (LOCAL)
GND (LOCAL)
VCC
VCC
700mV
VCC
PHASE for CHANNEL
TABLE 2.
2 WRT CHANNEL 1
VSENSE- (REMOTE)
10Ω
10Ω
31
180°
-60°
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
90°
0°
VSEN-
C
SEN
R
OS
VSEN+
OS_DA
R
REQUIRED
GAIN=1
FB
VSENSE+ (REMOTE)
37% VCC
53% VCC
REFIN
VCC
0.6V
ISL8120IRZEC
)
V
VMON
REF
Z
FB
OV/UV
COMP
V
in the loop, the differential amplifier’s input impedance
(R
and can be neglected when R
precision setpoint, R
resistors.
OS_DA
k*R
DIF
R
VDDQ
) is typically 500kΩ with a tolerance of 20% (R
FB
FIGURE 23. SIMPLIFIED DDR IMPLEMENTAION
should set to zero when the differential amplifier is
Z
ERROR AMP
INTERNAL SS
COMP
PHASE-SHIFTED
CLKOUT/REFIN
k
=
CLOCK
VDDQ
----------------- - 1
0.6V
COMP
OS
–
can be scaled by two paralleled
PGOOD
OS
0.6V
FB2
is less than 100Ω. To set a
PGOOD
VCC
700mV
VSEN2-
ISL8120IRZEC
MACHINE
STATE
E/A2
April 21, 2009
DIF
FN6763.1
%)