ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 25

• Manufacturer Part Number: ISL8120IRZ-T
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Current Loop
When the ISL8120IRZEC operates in 2-phase mode, the
current control loop keeps the channel’s current in balance.
After 175ns blanking period with respect to the falling edge
of the PWM pulse of each channel, the voltage developed
across the DCR of the inductor, r
MOSFETs, or a precision resistor, is filtered and sampled for
175ns. The current (I
resistor and provides feedback proportional to the average
output current of each channel.
For DCR sensing, the ICS can be derived from Equation 2:
ICS
VSEN2+
R
ISHARE
VSEN2-
ISET
=
ISET
IL DCR
------------------------ -
RISEN
•
VCC
I
AVG_CS
700mV
ISEN1B
R
VOUT
ISEN1
I
AVG_CS
+15µA
CS1
E/A
CURRENT
SHARE
BLOCK
FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION
/I
+15µA
CS2
IOUT1
C
L1
25
V
ISHARE
) is scaled by the R
PWM CONTROL
1.2V
CHANNEL 1
DS(ON)
ISEN1A
BLOCK
DCR1
DCR SENSING
R
COMP
AVG_OC
PHASE1
of the low-side
DCR1
AMP
I
CSH_ERR
SOFT-START AND
ISEN
7 CYCLES
FAULT LOGIC
CHANNEL 1
DELAY
CORRECTION
-
VOUT
CHANNEL 1
R
CURRENT
ISEN1
BLOCK
(EQ. 2)
ISL8120IRZEC
ISEN1B
I
CS1
-
I
AVG_CS
OC1
COMP
IOUT1
L1
+
I
ISEN1A
TRIP
r
DCR1
where IL is the inductor DC current, and DCR is its DC
resistance.
For low-side MOSFET r
derived from Equation 3:
In multiphase mode (VSEN2- pulled high), the scaled output
currents from both active channels are combined to create
an average current reference (I
average current of both channel outputs as calculated in
Equation 4.
DS(ON)
ICS
IAVG
= 105µA
=
SENSING
=
PHASE1
IL r
--------------------------------- -
+
I
TRIP
ICS1
-----------------------------------
•
RISEN
∑
∑
2
DS ON
=105µA
I
AVG
I
I
I
AVG
AVG_CS
CSH_ERR
+
2
(
+
ICS2
PHASE2
= (I
)
OC2
COMP
CS1
I
CS2
= I
= (V
AVG
+
-
-
+ I
DS(ON)
ISARE
CS2
or I
DCR2
AMP
CORRECTION
)/2
CS1
CHANNEL 2
CURRENT
- V
AVG
BLOCK
ISEN2A
sensing, the ICS can be
7 CYCLES
ISET
DELAY
DCR2
R
) which represents
)/G
CS
IOUT2
ISEN2B
SOFT-START AND
L2
C
FAULT LOGIC
PWM CONTROL
CHANNEL 2
CHANNEL 2
BLOCK
R
April 21, 2009
ISEN2
VOUT
FN6763.1
(EQ. 3)
(EQ. 4)