ISL6260CRZ Intersil, ISL6260CRZ Datasheet - Page 16

• Manufacturer Part Number: ISL6260CRZ
• Description: IC CORE REG MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6260CRZ

• Applications: Converter, Intel IMVP-6
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. This Table is
presented in its entirety in the Intel IMVP-6™ specification.
The ISL6260, ISL6260B will control the no-load output voltage
to an accuracy of ±0.5% over the range of 0.75V to 1.5V.
A fully-differential amplifier allows CPU die voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage
will droop from the VID table value by an amount
proportional to current to achieve the IMVP-6 load line. The
ISL6260 and ISL6260B provide for current to be measured
using resistors in series with the channel inductors as shown
in the application circuit of Figure 36 or using the intrinsic
series resistance of the inductors as shown in the application
circuit of Figure 35. In both cases, signals representing the
inductor currents are summed at VSUM which is the non-
inverting input to the DROOP amplifier shown in the block
diagram of Figure 37. The voltage at the DROOP pin minus
the output voltage, VO´ is thus a high-bandwidth analog of
the total inductor current. This value is used as an input to
the differential amplifier to achieve the IMVP-6 load line as
well as the input to the overcurrent circuit.
VID6
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6™
...
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID5
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
SPECIFICATION
VID4
0
0
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
VID3
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
16
VID2
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
VID1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
VID0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
1
ISL6260, ISL6260B
1.500V
1.4875
1.4375
1.4125
1.4000
1.2875
1.2000
1.1500
1.0000
0.9625
0.7500
0.6500
0.5000
VOUT
0.300
Off
Off
Off
Off
Off
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load-line
accuracy. Procedures to follow in determining component
values are covered in the “Component Selection and
Application” section of the datasheet.
In addition to the total current which is used for DROOP and
OC, the individual channel average currents are also
monitored and are used for balancing the load between the
channels. The IBAL circuit will adjust the channel pulse-
widths up or down relative to the other channels to cause the
voltages presented to the ISEN pins to be equal.
The ISL6260 and ISL6260B controller can be configured for
three-, two- or single-channel operation. To disable channel
two and/or channel three, its PWM output pin should be tied
to +5V VDD and the ISEN pins should be grounded. If the
ISL6208 gate driver is populated in an unused channel, its
PWM input pin should be opened in order to turn off its
output. In three-channel operation, the three channel PWM's
are 120 degrees apart, and in two-channel operation they
are 180 degrees apart. The channel PWM frequency is
determined by the value of RFSET as shown in the
“Component Selection and Application” section of this
document.
If the controller is kept in continuous conduction mode
(CCM), the switching frequency may not be constant but it
can maintain the switching ripple within spec. However, it will
be very close to the set value at high input voltage and
heavy load conditions. Selected by setting DPRSLPVR high,
DPRSTP# low, together with PSI# signal (see Table 2),
discontinuous conduction mode (DCM) is allowed. In DCM,
the ISL6260, ISL6260B commands the ISL6208 to turn off
the lower FET after its channel current decays to zero. As
load is further reduced, channel switching frequency will
drop, providing optimized efficiency even at light loading.
Dynamic Operation
Refer to Figure 39. The ISL6260 and ISL6260B respond to
changes in VID command voltage by slewing to new
voltages with a dV/dt set by the SOFT capacitor and by the
state of DPRSLPVR. With CSOFT = 20nF and DPRSLPVR
HIGH, the output voltage will move at ±2mV/µs for large
changes in voltage. For DPRSLPVR LOW, the large signal
dV/dt will be ±10mV/µs. As the output approaches the VID
command voltage, the dV/dt rate moderates to prevent
overshoot. During Geyserville III transitions where there is
one LSB VID step each 5µs, the controller will follow the VID
command with its dV/dt rate of ±2.5mV/µs.
January 3, 2006
FN9162.1