ISL6260CRZ Intersil, ISL6260CRZ Datasheet - Page 17

• Manufacturer Part Number: ISL6260CRZ
• Description: IC CORE REG MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6260CRZ

• Applications: Converter, Intel IMVP-6
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Keeping DPRSLPVR HIGH during VID transitions will result
in reduced dV/dt output voltage changes with resulting
minimized audio noise. For fastest recovery from Deeper
Sleep to Active mode, DPRSLPVR LOW achieves maximum
dV/dt. Therefore, the ISL6260 and ISL6260B are IMVP-6
compliant for DPRSTP# and DPRSLPVR logic.
Intersil's R
speed input voltage steps result in insignificant output
voltage perturbations. Refer to Figure 15 in the “Typical
Operating Performance” section of this document for Input
Transient Performance.
In response to load current step increases, the ISL6260 and
ISL6260B will transiently raise the switching frequency so
that response time is decreased and current is shared by all
the channels.
Modes of Operation Programmed by Logic Signals
The operational modes of ISL6260 and ISL6260B are
related to the control signals of DPRSLPVR, DPRSTP#, and
PSI#. ISL6260B responds PSI# signal by adding or dropping
PWM2 and adjusting the overcurrent protection level
accordingly. ISL6260 does not drop phases while in
operation. For example, if the ISL6260B is initially used as
three phase, the PSI# signal will add or drop PWM2 and
leave PWM1 and PWM3 always in operation. Meanwhile,
after PWM2 is dropped, the phase shift between the PWM1
and PWM3 is adjusted from 120 degree to 180 degree and
the overcurrent and the way-overcurrent protection level will
be adjusted to 2/3 of the initial value. If the ISL6260B is
initially used as two phase operation, it is suggested that
PWM1 and PWM2 pair, not PWM1 and PWM3 pair, should
be used such that PSI# signal will enable or disable PWM2
with PWM1 in operation always. The overcurrent and way-
overcurrent protection level in two-to-one phase mode
operation will be adjusted as two to one as well. For
ISL6260B, the DCM mode is independent of PSI#, it just
responds to the DPRSLPVR and DPRSTP#. The following
table shows the operation modes of ISL6260 and ISL6260B
with combinations of control logic.
FIGURE 39. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR
MSB of VID
DPRSTP#
PSI#
Vout
3
intrinsically has voltage-feed-forward. High-
DPRSLPVR’s EFFECT ON EXIT SLEW RATE
-2mV/us
17
2mV/us
10mV/us
ISL6260, ISL6260B
When PSI# is de-asserted low, ISEN2 pin is connected to
the ISEN pins of the operational phases internally to keep
proper current balance and less current overshoot and
undershoot when the disabled phase is enabled again.
Protection
The ISL6260 and ISL6260B provide overcurrent, overvoltage,
and undervoltage protection. Overcurrent protection is tied to
the voltage droop which is determined by the resistors
selected as described in the “Component Selection and
Application” section. After the load-line is set, the OCSET
resistor can be selected to detect overcurrent at any level of
droop voltage. For overcurrent less that twice the OCSET
level, the overload condition must exist for 120µs in order to
trip the OC fault latch. This is shown in Figure 28.
For overload exceeding twice the set level, the PWM outputs
will immediately shut off and PGOOD will go low to maximize
protection due to hard shorts. This protection was referred to
as way-overcurrent.
In addition, excessive phase unbalance due to gate driver
failure will be detected and will shut down the controller after
1ms. The phase unbalance is detected by the voltage on the
ISEN pins if the difference is greater than 9mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after 1ms in that condition.
The PWM outputs will turn off and PGOOD will go low. This
is shown in Figure 27. Note that most practical core
regulators will have the overcurrent set to trip before the -
300mV undervoltage limit.
There are two levels of overvoltage protection and response.
For output voltage exceeding the set value by +200mV for
1ms, a fault is declared. All of the above faults have the
same action taken: PGOOD is latched low and the upper
and lower power FETs are turned off so that inductor current
will decay through the FET body diodes. This condition can
be reset by bringing VR_ON low or by bringing VDD below
POR threshold. When these inputs are returned to their high
operating levels, a soft-start will occur.
IMVP-6
Logic
Other
Logic
TABLE 2. ISL6260 ISL6260B MODE OF OPERATIONS
DPRS
LPVR
0
0
1
1
0
0
1
1
STP# PSI#
DPR
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
0
N phase CCM N phase CCM
N phase CCM N-1 phase CCM Active
N phase CCM N phase DCM
N phase DCM N-1 phase DCM Deeper
N phase CCM N phase CCM
N phase CCM N-1 phase CCM
N phase CCM N phase CCM
N phase CCM N-1phase CCM
ISL6260
ISL6260B
January 3, 2006
FN9162.1
Active
Deeper
sleep
sleep
MODE
CPU