ISL6260CRZ Intersil, ISL6260CRZ Datasheet - Page 23

• Manufacturer Part Number: ISL6260CRZ
• Description: IC CORE REG MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6260CRZ

• Applications: Converter, Intel IMVP-6
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

less than 84mV, for example, 80mV. The new value will be
calculated by:
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the example above, the resistance on the DFB pin is Rdrp1
in parallel with Rdrop2, that is, 1K in parallel with 8.21K or
890Ω. The resistance on the VSUM pin is Rn in parallel with
RSeqv or 3.4K in parallel with 2.56K or 1460Ω. The
mismatch in the effective resistances is 1460-890 = 570Ω.
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1460/890 = 1.64.
Dynamic Mode of Operation - Dynamic Droop
using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the converter and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in the following equation:
Solving for Cn we now have the following equation:
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and Rs time constants as
given above, the transient performance will be optimum. As
in the Static Droop Case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.5μH, Cn is calculated below.
The value of this capacitor is selected to be 27nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the cap is too
Cn
Rdrp
-------------
DCR
Cn
L
=
=
------------------------------------------------ -
⎛
⎝
2
=
---------------------------------------- -
⎛
⎜
⎝
------------------------------------------ -
3.4kΩ
3.4kΩ
Rn
---------------------------------- -
Rn
_
⎛
⎜
⎝
Rn
---------------------------------- -
Rn
new
×
+
-------------
DCR
----------------- -
0.0012
0.5μH
RS
RS
×
+
L
×
+
RS
RS
2.56kΩ
2.56kΩ
EQV
EQV
=
EQV
EQV
84
80
⎞
⎟
⎠
mV
mV
⎞
⎟
⎠
⎞
⎠
×
=
Cn
(
28.5nF
Rdrp
23
1
+
Rdrp
2
)
−
Rdrp
1
ISL6260, ISL6260B
(EQ. 12)
(EQ. 13)
(EQ. 14)
small and vice versa. It is better to have the cap value a little
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the impedance
needs to be 2.1mΩ. The compensation design has to ensure
the output impedance of the converter be lower than 2.1mΩ.
There is a mathematical calculation file available to the user.
The power stage parameters such as L and Cs are needed
as the input to calculate the compensation component
values. Attention has be paid to the input resistor to the FB
pin. Too high of a resistor will cause an error to the output
voltage regulation because of bias current flowing in the FB
pin. It is better to keep this resistor below 3K when using this
file.
Static Mode of Operation - Current Balance using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6260 and ISL6260B
through the matching of the voltages present on the ISEN
pins. The ISL6260 and ISL6260B adjust the duty cycles of
each phase to maintain equal potentials on the ISEN pins.
RL and CL around each inductor, or around each discrete
current resistor, are used to create a rather large time
constant such that the ISEN voltages have minimal ripple
voltage and represent the DC current flowing through each
channel’s inductor. For optimum performance, RL is chosen
to be 10kΩ and CL is selected to be 0.22µF. When discrete
resistor sensing is used, a capacitor of 10nF should be
placed in parallel with RL to properly compensate the current
balance circuit.
ISL6260 and ISL6260B uses RC filter to sense the average
voltage on phase node and forces the average voltage on
the phase node to be equal for current balance. Even though
the ISL6260, ISL6260B forces the ISEN voltages to be
almost equal, the inductor currents will not be exactly equal.
Take DCR current sensing as example, two errors have to
be added to find the total current imbalance. 1) Mismatch of
DCR: If the DCR has a 5% tolerance then the resistors could
mismatch by 10% worst case. If each phase is carrying 20A
then the phase currents mismatch by 20A*10% = 2A. 2)
Mismatch of phase voltages/offset voltage of ISEN pins. The
January 3, 2006
FN9162.1