ISL59450IQZ Intersil, ISL59450IQZ Datasheet - Page 22

• Manufacturer Part Number: ISL59450IQZ
• Description: IC SWITCH VID CRSSPNT 128-MQFP
• Manufacturer: Intersil

Specifications of ISL59450IQZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bypass each reference voltage with a 0.01µF capacitor to
ground to reduce noise injection.
Outputs/Levels
Each signal output has a selectable gain of 0dB (GAIN 1) or
6dB (GAIN 2).
The input to the sync separators can be any of the video
inputs, as shown in the “Sync Separator Block Diagram” on
page 9. The HSYNC and VSYNC inputs are dedicated to
their respective sync separator (i.e. Sync Separator A can
connect to HSYNC
and VSYNC
Sync Separators
The ISL59450 contains two high performance video sync
separators that automatically lock to any SD and HD video
signal. They will also extract sync timing information from
non-standard video inputs and in the presence of
Macrovision pulses. Composite sync, vertical sync and
horizontal sync outputs are provided from each sync
separator. Timing is adjusted automatically for various video
standards. The composite sync output follows video in sync
pulses and a vertical sync pulse is output on the rising edge
of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
Component:
Pr/Pb
(YPrPb Mode)
Component:
Pr/Pb
(RGB Mode)
OUTPUT
VIDEO
TABLE 1. CHANNEL REFERENCE LEVELS (Continued)
TABLE 2. SUGGESTED REFERENCE LEVELS
V
V
V
V
REFERENCE
CHROMA
CHROMA
CHROMA
CHROMA
V
V
V
V
VSLICE
VSLICE
LUMA
LUMA
LUMA
LUMA
IN
VTIP
VTIP
B).
V
CHROMA
V
x1
x2
x1
x2
IN
IN
GAIN 1
LUMA
x1
x2
x1
x2
IN
IN
A
B
IN
IN
IN
IN
MASTER MODE
IN
A
B
IN
IN
IN
IN
A
A
B
B
A and VSYNC
A
A
B
B
x1
x1 V
CHROMA
V
22
GAIN 2
LUMA
x2
IN
x2 V
A, but not HSYNC
CHROMA
V
VOLTAGE
GAIN 1
LUMA
0.5
0.5
0.5
0.5
0.5
0.5
0.6
0.6
(V)
SLAVE MODE
1
1
1
1
x1
x1 V
CHROMA
V
GAIN 2
LUMA
IN
B
ISL59450
x2
x2
low for longer than the vertical sync default delay time. The
horizontal output gives horizontal timing with pre/post
equalizing pulses.
The use of two sync separators allows the user to send
independent sync information for two signals to downstream
devices. An example would be two video decoders or two
ADCs that are used in a picture-in-picture application. Each
sync separator is dedicated to its respective channel, Sync
Separator A for Channel A and Sync Separator B for
Channel B. It is important to note that the syncs for each
channel cannot be MUXed onto the other channel. For
example, HSYNC
HSYNC
See the “Sync Separator Timing Diagrams” beginning on
page 32 for typical horizontal and vertical sync output timing.
VERTICAL SYNC
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the ISL59450 on the first rising edge during the
vertical serration phase. In the absence of vertical serration
pulses, a vertical sync pulse will be forced out after the
vertical sync default delay time, approximately 60µs after the
last falling edge of the vertical equalizing phase.
HORIZONTAL SYNC
The horizontal circuit senses the composite sync edges and
produces the true horizontal pulses of nominal width 5µs for
standard definition NTSC signals. The pulse width of the
HSYNC output changes as the line frequency of the input
signal changes. For example, an NTSC input generates an
HSYNC
video input generates an HSYNC
1.9µs. The leading edge is triggered from the leading edge
of the input HSYNC with the same propagation delay as
composite sync. The half line pulses present in the input
signal during vertical blanking are removed with an internal
2H line eliminator circuit. This is a circuit that inhibits
horizontal output pulses until 75% of the line time is reached,
then the horizontal output operation is enabled again. Any
signals present on the I/P signal after the true H sync will be
ignored, thus the horizontal output will not be effected by
MacroVision copy protection. When there is a loss of sync,
the Horizontal Sync output is held high.
C
Connect external capacitors from C
ground. The C
as the Y5U general use capacitors may be too leaky and
cause faulty operation. The C
close to the C
board leakage. 56nF is recommended. The C
rectifies a 5µs pulse current and creates a voltage on C
SET
OUT
OUT
B and VSYNC
with a pulse width of 5µs; while a 720p HD
SET
SET
A and C
IN
capacitor should be a X7R grade or better
A and VSYNC
SET
OUT
SET
B pins to reduce possible
B.
OUT
IN
capacitor should be very
SET
A cannot be MUXed to
with a pulse width of
A and C
SET
SET
February 14, 2008
capacitor
B to
FN7510.0
SET
.