ISL59450IQZ Intersil, ISL59450IQZ Datasheet - Page 23

• Manufacturer Part Number: ISL59450IQZ
• Description: IC SWITCH VID CRSSPNT 128-MQFP
• Manufacturer: Intersil

Specifications of ISL59450IQZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The C
and V
Internal Control Registers
The ISL59450 is initialized and controlled by a set of internal
registers that define the operating parameters of the entire
device. Communication is established between the external
controller and the ISL59450 through a standard I
interface, as described earlier. The Register Listing table on
page 24 describes all of these registers. Detailed I
programming information for each register is described in
“ISL59450 Serial Communications” on page 33.
Note: Do not write to reserved registers. Reserved bits in
any register should be written with 0s, unless otherwise
noted.
INITIALIZATION
It is recommended that the registers are initialized to 0x00 by
toggling the Reset pin low after powering the device. Once
the registers are initialized, set bit 0 of Miscellaneous
Register 1 to one to engage the global enable and allow the
various channels to be powered up.
Logic Control Signals
Reset is a 5V digital Input, with 3.5V logic threshold and a
300k pull-down. Tie to +5V for normal operation. Taking
Reset to 0V and back to 5V initializes all data registers to
0x00.
Power-down is a digital input with 300k pull-down. When this
pin is taken high, all analog circuitry is disabled to minimize
power consumption. In Power-down mode, the outputs are
tri-stated while the I
register data is retained.
Crosstalk Issues
Do not set any one input to both A and B channels if the
references and modes for A and B are different. For
example, do not send CV
if the references for Channel A and Channel B are different
or if one channel is in slave mode while the other is in master
mode. This could cause clamping conflicts and compromise
performance.
Use the lowest bandwidth setting suitable for each
application to minimize noise, aliasing, and crosstalk. See
“Typical Application Curves” on page 19 and page 19.
SYNC
SET
voltage is converted to bias current for H
timing.
2
C interface remains active and all
IN
0 to both CV
23
OUT
A and CV
2
C host port
2
C
SYNC
OUT
B
ISL59450
Layout Issues
• Match channel-to-channel analog I/O trace lengths and
• All signal I/O lines should be routed over continuous
• Put the proper termination resistors as close to the device
• When testing, use high quality connectors and cables,
• Decouple well using a minimum of 2 power supply
Power Dissipation
With the high output drive capability of the ISL59450, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
PD
Where:
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing use Equation 2:
for sinking use Equation 3:
Where:
PD
PD
layout symmetry. This will minimize propagation delay
mismatches for S-video and component traces.
ground planes (i.e. no split planes or PCB gaps under
these lines).
as possible.
matching cable types and keep cable lengths to a
minimum.
decoupling capacitors (1000pF, 0.01µF), placed as close
to the devices as possible. Vias between the capacitor and
the device add unwanted inductance. Larger capacitors
can be farther away.
T
T
θ JA
V
I
V
R
I
MAX
SMAX
LOAD
AMAX
JMAX
MAX
MAX
S
OUT
LOAD
= Supply voltage
= Thermal resistance of the package
=
= Maximum output voltage of the application
=
=
= Load current
= Maximum quiescent supply current
= Maximum junction temperature
= Maximum ambient temperature
= Load resistance tied to ground
T
-------------------------------------------- -
V
V
JMAX
S
S
×
×
I
I
θ
SMAX
SMAX
–
JA
T
AMAX
+
+
(
(
V
V
S
OUT
–
V
–
OUT
V
S
)
)
×
×
V
--------------- -
I
LOAD
OUT
R
L
February 14, 2008
(EQ. 1)
(EQ. 2)
(EQ. 3)
FN7510.0