ISL59450IQZ Intersil, ISL59450IQZ Datasheet - Page 25

• Manufacturer Part Number: ISL59450IQZ
• Description: IC SWITCH VID CRSSPNT 128-MQFP
• Manufacturer: Intersil

Specifications of ISL59450IQZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Descriptions
ADDRESS
0x00
Sync Separator A
REGISTER
25
BIT(S)
1:0
2
3
4
5
6
7
Input Select A
Sync Type A
Sync Input Polarity A
Reserved
Enable A
Reserved
Sync Output Polarity A
ISL59450
FUNCTION NAME
This bit must be set to the type of incoming sync. For all
This bit must be set depending on the polarity of the
Chooses the sync source for Sync Separator A to
process. Use these bits in conjunction with the Sync
Type bit directly below.
00: Component SOG (Channel A)
01: S-Video SOG (Channel A)
10: Composite SOG (Channel A)
11: External H and V or CSYNC on H (Channel A)
SOG or CSYNC signals, this bit should be set.
0: HSYNC is on HSYNCA, VSYNC is on VSYNCA
1: SOG or CSYNC on HSYNCA
incoming sync.
0: SOG and active low external HSYNC/CSYNC.
1: Active high external, HSYNC/CSYNC signal.
This forces the internal polarity of the HSYNC signal to
be correct for clamping. Please note setting this bit also
inverts the polarity of HsyncA and VsyncA outputs. See
“Typical Register Settings” on page 31 for correct
values.
Set this bit to 0.
0: Sync Separator A is disabled
1: Sync Separator A is enabled
Set this bit to 0.
Polarity of HsyncA and VsyncA outputs
0: Active Low
1: Active High
Note: If the Field Invert Enable bit (register 0x14b1) is
set, FieldA’s output will also be inverted when this bit is
set.
DESCRIPTION
February 14, 2008
FN7510.0