ISL59450IQZ Intersil, ISL59450IQZ Datasheet - Page 26

• Manufacturer Part Number: ISL59450IQZ
• Description: IC SWITCH VID CRSSPNT 128-MQFP
• Manufacturer: Intersil

Specifications of ISL59450IQZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Descriptions
ADDRESS
0x01
0x02
Sync Separator B
Composite Channel A
REGISTER
26
(Continued)
BIT(S)
1:0
2:0
2
3
4
5
6
7
3
4
5
6
7
Input Select B
Sync Type B
Sync Input Polarity B
Reserved
Enable B
Reserved
Sync Output Polarity B
Input Select A
Filter Disable A
Output Amplifier Gain A 0: x1
Enable A
Low Offset Mode A
Slave Mode A
ISL59450
FUNCTION NAME
Chooses the sync source for Sync Separator B to
This bit must be set to the type of incoming sync. For all
This bit must be set depending on the polarity of the
0: CVBS
0: 7MHz Smoothing Filter
0: Normal Mode
0: Sync tip DC-restore on selected channel (master
process. Use these bits in conjunction with the Sync
Type bit directly below.
00: Component SOG (Channel B)
01: S-Video SOG (Channel B)
10: Composite SOG (Channel B)
11: External H and V or CSYNC on H (Channel B)
SOG or CSYNC signals, this bit should be set.
0: HSYNC is on HSYNCB, VSYNC is on VSYNCB
1: SOG or CSYNC on HSYNCB
incoming sync.
0: SOG and active low external HSYNC/CSYNC.
1: Active high external, HSYNC/CSYNC signal.
This forces the internal polarity of the HSYNC signal to
be correct for clamping. Please note setting this bit also
inverts the polarity of HsyncB and VsyncB outputs. See
“Typical Register Settings” on page 31 for correct
values.
Set this bit to 0.
0: Sync Separator B is disabled
1: Sync Separator B is enabled
Set this bit to 0.
Polarity of HsyncB and VsyncB outputs
0: Active Low
1: Active High
Note: If the Field Invert Enable bit (register 0x14b1) is
set, FieldB’s output will also be inverted when this bit is
set.
1: CVBS
2: CVBS
3: CVBS
4: CVBS
5: CVBS
1: Smoothing Filter bypassed (40MHz bandwidth)
1: x2
0: Disables (High-Z) Composite A output
1: Enables Composite output A
1: Low Offset Mode
Slightly lowers the DC offset from input to output by
increasing the maximum amount of clamp restore
current from 130µA to 270µA.
mode)
1: DC-restore clamp timing slaved to Sync Separator A
(slave mode)
IN
IN
IN
IN
IN
IN
0
1
2
3
4
5
DESCRIPTION
February 14, 2008
FN7510.0