ISL59450IQZ Intersil, ISL59450IQZ Datasheet - Page 33

• Manufacturer Part Number: ISL59450IQZ
• Description: IC SWITCH VID CRSSPNT 128-MQFP
• Manufacturer: Intersil

Specifications of ISL59450IQZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sync Separator HSYNC Timing for 720p
ISL59450 Serial Communications
I
The ISL59450 uses a 2-wire I
communication with its host. SCL is the Serial Clock line,
driven by the host, and SDA is the Serial Data line, which
can be driven by all devices on the bus. SDA is open drain to
allow multiple devices to share the same bus
simultaneously.
Communication is accomplished in three steps:
The ISL59450 has a 7-bit address on the serial bus. The upper
6-bits are permanently set to 100010x, with the x determined by
the state of the Address pin (Table 3). This allows two
2
td
t
td
t
1. The Host selects the ISL59450 with which it wishes to
2. The Host writes the initial ISL59450 Configuration
3. The Host writes to or reads from the ISL59450’s
HOUT
HOUT
C Overview
PARAMETER
HOUT
PARAMETER
HOUT
communicate.
Register address it wishes to write to or read from.
Configuration Register. The ISL59450’s internal address
pointer auto increments, so to read registers 0x00
through 0x16, for example, one would write 0x00 in step
two, then repeat step four 28 times, with each read
returning the next register value.
CONDITIONS: V
SYNCIN
HOUT Timing Relative to Input
Horizontal Output Width
HOUT Timing Relative to Input
Horizontal Output Width
D
= 3.3V T
H
OUT
33
2
C serial bus for
DESCRIPTION
DESCRIPTION
A
= +25°C
td
HOUT
ISL59450
t
HOUT
ISL59450s to be independently controlled while sharing the
same bus. The Address pin has an internal pull-down resistor
to pull the terminal low to set a zero.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 34).
The ISL59450 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 35).
(MSB)
B7
A6
1
1
B6
A5
CONDITIONS
CONDITIONS
0
0
TABLE 3. I
B5
A4
0
0
B4
A3
0
0
2
C ADDRESS OPTIONS
B3
A2
0
0
B2
A1
1
1
(Address) R/W
B1
A0
0
1
@ 3.3V
TYP
1.90
TYP
200
90
5
B0
1/0 0x85/0x84
1/0 0x87/0x86
February 14, 2008
HEX
UNIT
UNIT
FN7510.0
µs
ns
µs
ns