AC162078 Microchip Technology, AC162078 Datasheet
AC162078
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... High-Performance Microcontrollers with 10-bit A/D and nanoWatt Technology 2009 Microchip Technology Inc. PIC18F1230/1330 Data Sheet DS39758D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Instructions PIC18F1230 4096 2048 PIC18F1330 8192 4096 2009 Microchip Technology Inc. PIC18F1230/1330 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Programmable External Interrupts • Four Input Change Interrupts • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator ...
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... RA6/OSC2/CLKO/T1OSO / RB7/PWM5/PGD 7 12 RB6/PWM4/PGC 8 11 RB5/PWM3 9 RB4/PWM2 RB3/INT3/KBI3/CMP1/T1OSI 2 19 RB2/INT2/KBI2/CMP2/T1OSO 3 18 RA7/OSC1/CLKI/T1OSI 4 17 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD 8 13 RB6/PWM4/PGC 9 12 RB5/PWM3 RB4/PWM2 10 11 (1) (1) (1) /T1CKI (1) (2) /FLTA (1) (1) /T1CKI /AN3 (1) (1) (1) /T1CKI (1) (2) /FLTA (1) (1) /T1CKI /AN3 2009 Microchip Technology Inc. ...
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... Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of Note 1: CONFIG3H. Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H recommended that the user connect the center metal pad for this device package to the ground. 3: 2009 Microchip Technology Inc. PIC18F1230/1330 ...
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... Appendix A: Revision History............................................................................................................................................................. 303 Appendix B: Device Differences......................................................................................................................................................... 304 Appendix C: Conversion Considerations ........................................................................................................................................... 305 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 305 Appendix E: Migration from Mid-Range TO Enhanced Devices ........................................................................................................ 306 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 306 Index .................................................................................................................................................................................................. 307 DS39758D-page 6 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2009 Microchip Technology Inc. PIC18F1230/1330 DS39758D-page 7 ...
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... PIC18F1230/1330 NOTES: DS39758D-page 8 2009 Microchip Technology Inc. ...
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... Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 23.0 “Electrical Characteristics” for values. 2009 Microchip Technology Inc. PIC18F1230/1330 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES ...
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... Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F1330), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF1330), function over an extended V range of 2.0V to 5.5V. DD 2009 Microchip Technology Inc. for ...
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... Interrupt Sources I/O Ports Timers Power Control PWM Module Serial Communications 10-Bit Analog-to-Digital Module Resets (and Delays) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages 2009 Microchip Technology Inc. PIC18F1230/1330 PIC18F1230 DC – 40 MHz 4096 2048 256 128 17 Ports Channels ...
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... A/D Converter USART PORTA RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1 RA2/TX/CK RA3/RX/DT RA4/T0CKI/AN2/V + REF MCLR/V /RA5 (1) /FLTA (4) PP (2) (2) RA6/OSC2 /CLKO / T1OSO (3) /T1CKI (3) /AN3 (2) (2) RA7/OSC1 /CLKI / T1OSI (3) /FLTA (4) PORTB RB0/PWM0 RB1/PWM1 RB2/INT2/KBI2/CMP2/ T1OSO (3) /T1CKI (3) RB3/INT3/KBI3/CMP1/ (3) T1OSI RB4/PWM2 8 RB5/PWM3 8 RB6/PWM4/PGC RB7/PWM5/PGD 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX CONFIG3H. 2009 Microchip Technology Inc. PIC18F1230/1330 Pin Buffer Type Type QFN 1 Master Clear (input), programming voltage (input) or Fault detect input ...
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... EUSART synchronous clock. 8 I/O TTL Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data. 28 I/O TTL Digital I/ Timer0 external clock input. I Analog Analog input 2. I Analog A/D reference voltage (high) input. CMOS = CMOS compatible input or output I = Input P = Power Description 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX CONFIG3H. 2009 Microchip Technology Inc. PIC18F1230/1330 Pin Buffer Type Type QFN PORTB is a bidirectional I/O port. ...
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... P — Positive supply for logic and I/O pins — Ground reference for A/D Converter module — Positive supply for A/D Converter module — — No Connect. 11, 14, 18, 22, 25 CMOS = CMOS compatible input or output I = Input P = Power Description 2009 Microchip Technology Inc. ...
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... The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS ( MCLR ...
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... V DD Not all devices incorporate software BOR Note: control. See Section 5.0 “Reset” for device-specific information. may result in a spontaneous DD does not approach the set point. DD and circuit as the microcontroller 2009 Microchip Technology Inc. ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2009 Microchip Technology Inc. PIC18F1230/1330 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel resonant crystal. Use of a series resonant crystal may give Note: a frequency out of manufacturer’s specifications. 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 3-1: ( (1) Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2. ...
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... FIGURE 3-4: Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) 2009 Microchip Technology Inc. ...
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... Recommended values: 3 k R 100 k EXT C > EXT 2009 Microchip Technology Inc. PIC18F1230/1330 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Two compensation techniques are discussed in Section 3.6.5.1 EUSART” and Section 3.6.5.2 “Compensating with the Timers”, but other techniques may be used. or temperature changes, which can “Compensating with the 2009 Microchip Technology Inc. ...
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... OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 TUN4 ...
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... OSCTUNE<7> LP, XT, HS, RC, EC Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up 2009 Microchip Technology Inc. ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. 2009 Microchip Technology Inc. PIC18F1230/1330 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 2: Default output frequency of INTOSC on Reset. 3: DS39758D-page 28 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown 2009 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. Note: 2009 Microchip Technology Inc. PIC18F1230/1330 time clock. Other features may be operating that do not require a device clock source (i.e., INTx pins and others). Peripherals that may add significant current consumption are listed in Section 23.0 “ ...
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... PIC18F1230/1330 NOTES: DS39758D-page 30 2009 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 4.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: power • ...
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... Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. 2009 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2009 Microchip Technology Inc. PIC18F1230/1330 n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC OST (1) T (1) T PLL 1 2 n-1 n Clock Transition (2) PC OSTS bit Set ; (approx). These intervals are not shown to scale. PLL . OSC 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. Note1:T OST OSC PLL 2009 Microchip Technology Inc. PIC18F1230/1330 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD 2009 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2009 Microchip Technology Inc. PIC18F1230/1330 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... None LP, XT OST HSPLL T OST EC CSD (1) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (4) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 5-2 for time-out situations. 2009 Microchip Technology Inc. PIC18F1230/1330 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39758D-page 40 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown 2009 Microchip Technology Inc. ...
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... Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hard- ware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 5- ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. 2009 Microchip Technology Inc. ...
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... Power-up Timer (PWRT) delay. Note the nominal time required for the PLL to lock. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 5.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39758D-page 44 T PWRT T OST T PWRT T OST T PWRT T OST 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. Note: OST max. First three stages of the PWRT timer. T PLL 2009 Microchip Technology Inc. PIC18F1230/1330 , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF 2009 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read as ‘0’. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: 2009 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, WDT Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read as ‘0’. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: 2009 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, WDT Reset, ...
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... Wake-up via WDT or Interrupt ---- uuuu (6) (6) -uuu -uuu (6) (6) -uuu -uuu uuuu u-uu uuuu uuuu --uu uuuu --uu uuuu uuuu uuuu (5) (5) uuuu uuuu 2009 Microchip Technology Inc. ...
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... Reset Vector High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector On-Chip Program Memory Read ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 can return these values to Stack Pointer STKPTR<4:0> 00010 2009 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software POR. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 “Table Reads and Table Writes”. COMPUTED GOTO USING AN OFFSET VALUE 2009 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2009 Microchip Technology Inc. PIC18F1230/1330 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code address embedded into the Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2009 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” provides a detailed description of the Access RAM. 2009 Microchip Technology Inc. PIC18F1230/1330 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh 2009 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, 2009 Microchip Technology Inc. PIC18F1230/1330 7 Data Memory ...
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... F91h PDC0L F90h PDC0H F8Fh PDC1L F8Eh PDC1H F8Dh PDC2L F8Ch PDC2H F8Bh FLTCONFIG F8Ah LATB F89h LATA F88h SEVTCMPL (1) F87h SEVTCMPH F86h PWMCON0 F85h PWMCON1 F84h DTCON F83h OVDCOND F82h OVDCONS F81h PORTB F80h PORTA 2009 Microchip Technology Inc. ...
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... Bit 7 and bit 6 are cleared by user software POR. 5: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: This bit has no effect if the Configuration bit, WDTEN, is enabled. 7: 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — ...
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... CMP0IP TMR1IP 49, 102 -111 1111 CMP0IF TMR1IF 49, 98 -000 0000 CMP0IE TMR1IE 49, 100 -000 0000 TUN1 TUN0 49, 25 00-0 0000 PTMOD1 PTMOD0 49, 122 0000 0000 — — 49, 122 00-- ---- 2009 Microchip Technology Inc. ...
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... When disabled, these bits read as ‘0’. Bit 7 and bit 6 are cleared by user software POR. 5: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: This bit has no effect if the Configuration bit, WDTEN, is enabled. 7: 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 4 Bit 3 Bit 2 — — ...
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... Table 22-2 and Table 22-3. The C and DC bits operate as the borrow Note: and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown 2009 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. 2009 Microchip Technology Inc. PIC18F1230/1330 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory 2009 Microchip Technology Inc. ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 2009 Microchip Technology Inc. PIC18F1230/1330 6.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... F00h Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h Bank 1 001001da through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory 2009 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... Bank 0 addresses below 5Fh can still be addressed F80h by using the BSR. FFFh 2009 Microchip Technology Inc. PIC18F1230/1330 Remapping of the Access Bank applies only to operations using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. ...
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... PIC18F1230/1330 NOTES: DS39758D-page 70 2009 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2009 Microchip Technology Inc. PIC18F1230/1330 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. The EEIF interrupt flag bit (PIR2<4>) is set Note: when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT 2009 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-x R/W-0 ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE ERASE TBLPTR<21:6> TABLE WRITE TBLPTR<21:3> TABLE READ – TBLPTR<21:0> TBLPTRL 0 2009 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD 2009 Microchip Technology Inc. PIC18F1230/1330 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2009 Microchip Technology Inc. ...
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... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. 2009 Microchip Technology Inc. PIC18F1230/1330 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
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... TBLWT holding register. ; loop until buffers are full 2009 Microchip Technology Inc. ...
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... OSCFIF — PIE2 OSCFIE — — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Legend: 2009 Microchip Technology Inc. PIC18F1230/1330 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ...
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... PIC18F1230/1330 NOTES: DS39758D-page 80 2009 Microchip Technology Inc. ...
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... Characteristics”) for exact limits. 8.1 EEADR Register The EEPROM Address register can address 256 bytes of data EEPROM. 2009 Microchip Technology Inc. PIC18F1230/1330 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same range ...
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... When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition. Note 1: DS39758D-page 82 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown 2009 Microchip Technology Inc. ...
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... BTFSC EECON1, WR BRA $-2 SLEEP BCF EECON1, WREN 2009 Microchip Technology Inc. PIC18F1230/1330 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
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... Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR WREN — EEIP — LVDIP — EEIF — LVDIF — EEIE — LVDIE Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF — — 49 — — 49 — — 49 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2009 Microchip Technology Inc. PIC18F1230/1330 EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... WREG ; ADDWFC RES3 BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : 2009 Microchip Technology Inc ...
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... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). 2009 Microchip Technology Inc. PIC18F1230/1330 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...
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... LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Oscillator crystal input or external clock source input. I ANA External clock source input. I ANA Timer1 oscillator input Fault detect input for PWM. Description 2009 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 ...
Page 90
... The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTA and PORTB are used for the interrupt- on-change feature. Polling of PORTA and PORTB is not recommended while using the interrupt-on-change feature. PORTB is and will end the mis- CY 2009 Microchip Technology Inc. ...
Page 91
... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default Note 1: when PBADEN is set and digital inputs when PBADEN is cleared. Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 I/O I/O Type ...
Page 92
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. DS39758D-page 92 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF C0OUT — — CMEN2 Reset Bit 1 Bit 0 Values on Page: RB1 RB0 INT0IF RBIF 47 INT3IP RBIP 47 INT2IF INT1IF 47 CMEN1 CMEN0 48 2009 Microchip Technology Inc. ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. 2009 Microchip Technology Inc. PIC18F1230/1330 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...
Page 94
... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 95
... None of the RB7:RB4 pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. 2009 Microchip Technology Inc. PIC18F1230/1330 Interrupt flag bits are set when an interrupt Note: ...
Page 96
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39758D-page 96 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 97
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 ...
Page 98
... R-0 R/W-0 R/W-0 TXIF CMP2IF CMP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009 Microchip Technology Inc. Enable bit, GIE should ensure the R/W-0 R/W-0 CMP0IF TMR1IF ...
Page 99
... PWM time base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software PWM time base has not matched the value in PTPER register bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIF — ...
Page 100
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39758D-page 100 R-0 R/W-0 R/W-0 TXIE CMP2IE CMP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009 Microchip Technology Inc. R/W-0 R/W-0 CMP0IE TMR1IE bit Bit is unknown ...
Page 101
... Unimplemented: Read as ‘0’ bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PWM enabled 0 = PWM disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIE — LVDIE U = Unimplemented bit, read as ‘0’ ...
Page 102
... CMP0 is low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39758D-page 102 R/W-1 R/W-1 R/W-1 TXIP CMP2IP CMP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 CMP0IP TMR1IP bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 104
... The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 5.1 “RCON Register”. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 105
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2009 Microchip Technology Inc. PIC18F1230/1330 11.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 106
... PIC18F1230/1330 NOTES: DS39758D-page 106 2009 Microchip Technology Inc. ...
Page 107
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2009 Microchip Technology Inc. PIC18F1230/1330 Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. ...
Page 108
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks Delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2009 Microchip Technology Inc. ...
Page 109
... RA7 RA6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in CONFIG1H. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 12.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 110
... PIC18F1230/1330 NOTES: DS39758D-page 110 2009 Microchip Technology Inc. ...
Page 111
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H. 2009 Microchip Technology Inc. PIC18F1230/1330 Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN) ...
Page 112
... F /4 OSC (1) Oscillator Internal 0 Clock T1CKPS1:T1CKPS0 TMR1CS 8 TMR1L TMR1ON On/Off T1SYNC 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 Synchronize Prescaler det 2 Peripheral Clocks 2009 Microchip Technology Inc. ...
Page 113
... Capacitor values are for design guidance only. 2009 Microchip Technology Inc. PIC18F1230/1330 13.2.1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the System Clock Select bits, SCS1:SCS0 (OSCCON< ...
Page 114
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 2009 Microchip Technology Inc. ...
Page 115
... Timer1 Register High Byte T1CON RD16 T1RUN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2009 Microchip Technology Inc. PIC18F1230/1330 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 116
... PIC18F1230/1330 NOTES: DS39758D-page 116 2009 Microchip Technology Inc. ...
Page 117
... Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors 2009 Microchip Technology Inc. PIC18F1230/1330 The PWM module has the following features: • six PWM I/O pins with three duty cycle generators. Pins can be paired to acquire a complete half-bridge control ...
Page 118
... Override Logic PWM Channel 1 Generator 1 Dead-Time Generator and Override Logic PWM Channel 0 Generator 0 Dead-Time Generator and Override Logic Special Event Postscaler PTDIR PWM5 PWM4 (1) PWM3 Output PWM2 Driver Block PWM1 PWM0 FLTA Special Event Trigger 2009 Microchip Technology Inc. ...
Page 119
... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pins. For example, PWM0 will be the complement of PWM1 and PWM2 will be the complement of PWM3. The dead-time generator 2009 Microchip Technology Inc. PIC18F1230/1330 V DD Dead-Band ...
Page 120
... The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. The PTMR register pair (PTMRL:PTMRH) Note: is not cleared when the PTEN bit is cleared in software. 2009 Microchip Technology Inc. ...
Page 121
... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates 2009 Microchip Technology Inc. PIC18F1230/1330 PTMR Clock Timer Reset Up/Down Zero Match Timer ...
Page 122
... OSC /256 (1:64 prescale) OSC U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PTMOD1 PTMOD0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 123
... PWM I/O pin pair (PWM2, PWM3 the Complementary mode For PMOD2 PWM I/O pin pair (PWM4, PWM5 the Independent mode 0 = PWM I/O pin pair (PWM4, PWM5 the Complementary mode Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 (1) (1) R/W-1 U-0 ...
Page 124
... Output overrides via the OVDCON register are synchronized to the PWM time base 0 = Output overrides via the OVDCON register are asynchronous DS39758D-page 124 R/W-0 R/W-0 U-0 SEVOPS0 SEVTDIR — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 UDIS OSYNC bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 125
... Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset The PTMR register is not cleared when Note: PTCONx is written. 2009 Microchip Technology Inc. PIC18F1230/1330 Table 14-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. ...
Page 126
... PWM time base begins to count upwards. The postscaler selection bits may be used in this Timer mode to reduce the frequency of the interrupt events. Figure 14-7 shows the interrupts in Continuous Up/ Down Count mode 001h 002h 001h 002h Up/Down Count mode 2009 Microchip Technology Inc. ...
Page 127
... PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE PRESCALER = 1 OSC 002h PTMR PTDIR bit PTMR_INT_REQ 1 1 PTIF bit PRESCALER = 1 PTMR 002h PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2009 Microchip Technology Inc. PIC18F1230/1330 FFFh 000h FFFh 000h ...
Page 128
... Note: PTEN is active. It will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load PTMOD bits with required data and then set PTEN 3FEh 3FFh 001h 000h 3FEh 3FDh 001h 002h 2009 Microchip Technology Inc. ...
Page 129
... The PWM frequency is the inverse of period; or EQUATION 14-3: PWM FREQUENCY 1 PWM Frequency = PWM Period 2009 Microchip Technology Inc. PIC18F1230/1330 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 14-4: PWM RESOLUTION ...
Page 130
... PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODES New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39758D-page 130 Period Value Loaded from PTPER Buffer Register New Value Written to PTPER Buffer Period Value Loaded from PTPER Buffer Register New Value Written to PTPER Buffer 2009 Microchip Technology Inc. ...
Page 131
... duty cycle match occurs duty cycle match occurs duty cycle match occurs on Q4 2009 Microchip Technology Inc. PIC18F1230/1330 PTMR and the lower 2 bits are equal to Q1, Q2 Q4, depending on the lower two bits of the PDCx (when the prescaler is 1:1 or PTCKPS<1:0> = 00) ...
Page 132
... PTPER register. FIGURE 14-12: PTPER PTMR PDCx (old) Value PDCx (new) 0 Duty Cycle Active at Beginning Period of Period Duty Cycle Value Loaded from Buffer Register New Value Written to Duty Cycle Buffer EDGE-ALIGNED PWM New Duty Cycle Latched 2009 Microchip Technology Inc. ...
Page 133
... Duty Cycle Start of First PWM Period 2009 Microchip Technology Inc. PIC18F1230/1330 Duty Cycle Value Loaded from Buffer Register New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
Page 134
... The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets. are the TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS 3-Phase Load 2009 Microchip Technology Inc. ...
Page 135
... DEAD-TIME INSERTION FOR COMPLEMENTARY PWM PDC1 Compare Output PWM1 PWM0 2009 Microchip Technology Inc. PIC18F1230/1330 14.7.1 DEAD-TIME INSERTION Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead- time insertion. As shown in Figure 14-17, each dead- time unit has a rising and falling edge detector connected to the duty cycle comparison output ...
Page 136
... OSC caler is set to 1:1, the dead-time counter is clocked by the Q clock corresponding to the Q clocks on which the PWM duty cycle match occurs. R/W-0 R/W-0 DT1 DT0 bit Bit is unknown /4, OSC /16, F /64, F /256 OSC OSC OSC /4) OSC /4, OSC 2009 Microchip Technology Inc. ...
Page 137
... OSC 4 /16 OSC 2009 Microchip Technology Inc. PIC18F1230/1330 14.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM mod- ule ...
Page 138
... The even channel is always the complement of the odd channel, with dead-time inserted, before the odd channel can be driven to its active state as shown in Figure 14-20. 2: Dead time inserted in the PWM channels even when they are in Override mode. 2009 Microchip Technology Inc. ...
Page 139
... Odd override bit is activated which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time. 2009 Microchip Technology Inc. PIC18F1230/1330 DS39758D-page 139 ...
Page 140
... Bit is cleared R/W-0 R/W-0 R/W-0 POUT4 POUT3 POUT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) control the commutation R/W-1 R/W-1 POVD1 POVD0 bit Bit is unknown R/W-0 R/W-0 POUT1 POUT0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 141
... PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 2009 Microchip Technology Inc. PIC18F1230/1330 14.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin 5 6 control defined in the CONFIG3L register. They are: • ...
Page 142
... PWM outputs. 14.12.1 FAULT PIN ENABLE BIT By setting the bit FLTAEN in the FLTCONFIG register, the corresponding Fault input is enabled. If FLTAEN bit is cleared, then the Fault input has no effect on the PWM module I/O pin TTL or Schmitt Trigger 2009 Microchip Technology Inc. ...
Page 143
... Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is cleared by the user only bit 0 FLTAEN: Fault A Enable bit 1 = Enable Fault Disable Fault A 2009 Microchip Technology Inc. PIC18F1230/1330 14.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., FLTA input is active), the PWM output signals are driven into their inactive states ...
Page 144
... The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler configured by writing the SEVOPS3:SEVOPS0 control bits in the PWMCON1 register. The Special Event Trigger output postscaler is cleared on any write to the SEVTCMP register pair any device Reset. 2009 Microchip Technology Inc. ...
Page 145
... Shaded cells are not used with the Power Control PWM. Legend: Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. Note 1: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 TMR0IE ...
Page 146
... PIC18F1230/1330 NOTES: DS39758D-page 146 2009 Microchip Technology Inc. ...
Page 147
... Break Character Transmission • Synchronous – Master (half-duplex) with Selectable Clock Polarity • Synchronous – Slave (half-duplex) with Selectable Clock Polarity 2009 Microchip Technology Inc. PIC18F1230/1330 The pins of the Enhanced USART are multiplexed with PORTA. In order to configure RA2/TX/CK and RA3/RX/ EUSART: • ...
Page 148
... Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. Note 1: DS39758D-page 148 R/W-0 R/W-0 R/W-0 (1) SYNC SENDB BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-1 R/W-0 TRMT TX9D bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 149
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R-0 CREN ...
Page 150
... Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39758D-page 150 R/W-0 R/W-0 U-0 TXCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 151
... Legend Don’t care value of SPBRGH:SPBRG register pair 2009 Microchip Technology Inc. PIC18F1230/1330 Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. ...
Page 152
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39758D-page 152 Bit 5 Bit 4 Bit 3 Bit 2 TXEN SYNC SENDB BRGH SREN CREN ADDEN FERR TXCKP BRG16 — Reset Values Bit 1 Bit 0 on Page: TRMT TX9D 48 OERR RX9D 48 WUE ABDEN 2009 Microchip Technology Inc. ...
Page 153
... Microchip Technology Inc. PIC18F1230/1330 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) — ...
Page 154
... Error (decimal) (K) (decimal) 8332 0.300 -0.01 6665 2082 1.200 -0.04 1665 1040 2.400 -0.04 832 259 9.615 -0.16 207 129 19.230 -0.16 103 42 57.142 0. 117.647 -2.12 16 SPBRG value (decimal) 832 207 103 25 12 — — 2009 Microchip Technology Inc. ...
Page 155
... RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. 2009 Microchip Technology Inc. PIC18F1230/1330 Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character ...
Page 156
... ABDEN bit RX pin ABDOVF bit BRG Value XXXXh DS39758D-page 156 Edge #2 Edge #3 Edge #1 bit 1 bit 3 Start bit 0 bit 2 bit 4 XXXXh XXXXh Start bit 0 0000h 001Ch Edge #4 Edge #5 bit 5 bit 7 Stop bit bit 6 Auto-Cleared 1Ch 00h FFFFh 0000h 2009 Microchip Technology Inc. ...
Page 157
... Sampling Circuit • Asynchronous Transmitter • Asynchronous Receiver • Auto-Wake-up on Sync Break Character • 12-Bit Break Character Transmit • Auto-Baud Rate Detection 2009 Microchip Technology Inc. PIC18F1230/1330 15.2.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR) ...
Page 158
... TSR Register TRMT TX9 TX9D bit 0 bit 1 Word 1 bit 0 bit 1 bit 7/8 Word Pin Buffer and Control TX pin SPEN bit 7/8 Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. 2009 Microchip Technology Inc. ...
Page 159
... SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 160
... CPU. CREN OERR 64 RSR Register MSb or 16 Stop ( 4 RX9 Data Recovery RX9D RCREG Register Interrupt RCIF RCIE 2009 Microchip Technology Inc. FERR LSb 1 0 Start FIFO 8 Data Bus ...
Page 161
... Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) 2009 Microchip Technology Inc. PIC18F1230/1330 Start Stop bit 7/8 ...
Page 162
... If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Cleared Due to User Read of RCREG Cleared Due to User Read of RCREG Sleep Ends 2009 Microchip Technology Inc. Auto-Cleared Auto-Cleared Note 1 ...
Page 163
... TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here SENDB (Transmit Shift Reg. Empty Flag) 2009 Microchip Technology Inc. PIC18F1230/1330 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer ...
Page 164
... Start transmission by loading data to the TXREG register using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set bit 1 bit 2 bit 7 bit 0 Word 1 ), the TXREG is empty and CY bit 1 bit 7 Word 2 ‘ 1’ 2009 Microchip Technology Inc. ...
Page 165
... SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 bit 2 bit 0 bit 1 Bit 5 ...
Page 166
... CREN ADDEN FERR TXEN SYNC SENDB BRGH RXDTP TXCKP BRG16 bit 5 bit 6 bit 7 ‘0’ Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 47 CMP0IF TMR1IF 49 CMP0IE TMR1IE 49 CMP0IP TMR1IP 49 OERR RX9D 48 48 TRMT TX9D 48 — WUE ABDEN 2009 Microchip Technology Inc. ...
Page 167
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 To set up a Synchronous Slave Transmission: 1. ...
Page 168
... RCIP TXIP CMP2IP CMP1IP SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH RXDTP TXCKP BRG16 — Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 47 CMP0IF TMR1IF 49 CMP0IE TMR1IE 49 CMP0IP TMR1IP 49 OERR RX9D 48 48 TRMT TX9D 48 WUE ABDEN 2009 Microchip Technology Inc. ...
Page 169
... A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled 2009 Microchip Technology Inc. PIC18F1230/1330 The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins. The ADCON2 register, shown in Register 16-3, configures the A/D clock source, programmed acquisition time and justification ...
Page 170
... PCFG0: A/D Port Configuration bit for RA0/AN0 0 = Port is configured as AN0 1 = Port is configured as RA0 DS39758D-page 170 R/W-0 R/W-0 R/W-0 VCFG0 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + source) REF + REF DD R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 171
... F /2 OSC If the A/D F clock source is selected, a delay of one T Note 1: RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 172
... A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 16-1. V AIN (Input Voltage) VCFG0 REF result is loaded into the CHS1:CHS0 0011 AN3 0010 AN2 0001 AN1 0000 AN0 2009 Microchip Technology Inc. ...
Page 173
... SS = Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS 2009 Microchip Technology Inc. PIC18F1230/1330 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
Page 174
... T based on assumptions: C HOLD . The sampling Rs Conversion Error V DD Temperature (- HOLD ln(1/2048) S COFF ) ln(1/2047) the minimum acquisition time, . This calculation is ACQ the following application system = 2.5 k 1/2 LSb 5V k 85C (system max ms. 2009 Microchip Technology Inc. ...
Page 175
... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D 3: accuracy may be out of specification. Low-power (PIC18LF1230/1330) devices only. 4: 2009 Microchip Technology Inc. PIC18F1230/1330 16.4 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
Page 176
... Analog levels on a digitally configured converted. 2: Analog levels on any pin defined as a digital input may cause the digital input clock to buffer to consume current out of the RC device’s specification limits. OH input will be accurately 2009 Microchip Technology Inc. ...
Page 177
... Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) 2009 Microchip Technology Inc. PIC18F1230/1330 After the A/D conversion is completed or aborted wait is required before the next acquisition can AD be started. After this wait, acquisition on the selected channel is automatically started ...
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... CHS1 CHS0 — VCFG0 PCFG3 PCFG2 ACQT2 ACQT1 ACQT0 ADCS2 (2) RA5 RA4 RA3 RA2 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 47 CMP0IF TMR1IF 49 CMP0IE TMR1IE 49 CMP0IP TMR1IP GO/DONE ADON 48 PCFG1 PCFG0 48 ADCS1 ADCS0 48 RA1 RA0 50 49 2009 Microchip Technology Inc. ...
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... Comparator 1 is disabled bit 0 CMEN0: Comparator 0 Enable bit 1 = Comparator 0 is enabled 0 = Comparator 0 is disabled 2009 Microchip Technology Inc. PIC18F1230/1330 Section 18.0 Module”). The digital outputs are not available at the pin level and can only be read through the control register, CMCON (Register 17-1). CMCON also selects the comparator input ...
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... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMPxIF. c) Input returning to original state. A mismatch condition will continue to set flag bit CMPxIF. Reading CMCON will end the mismatch condition and allow flag bit CMPxIF to be cleared. the 2009 Microchip Technology Inc. ...
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... LEAKAGE 2009 Microchip Technology Inc. PIC18F1230/1330 17.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between ...
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... PORTA Data Latch Register (Read and Write to Data Latch) PORTA Data Direction Control Register RB5 RB4 RB3 RB2 Reset Bit 1 Bit 0 Values on Page: CMEN1 CMEN0 48 CVR1 CVR0 48 INT0IF RBIF 47 CMP0IF TMR1IF 49 CMP0IE TMR1IE 49 CMP0IP TMR1IP 49 RA1 RA0 RB1 RB0 2009 Microchip Technology Inc. ...
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... If CVRR = (CV x 1/4) + (((CVR3:CVR0)/32) x REF RSRC CV ) RSRC 2009 Microchip Technology Inc. PIC18F1230/1330 The comparator reference supply voltage can come from either AV multiplexed with RA4 and AV selected by the CVRSS bit (CVRCON<4>). Additionally, the voltage reference can select the unscaled V REF bypassing the CV Figure 18-1 ...
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... CV /32 step size (high range) RSRC RSRC Source Selection bit REF = (V +) – (AV RSRC REF = AV – AV RSRC DD SS Value Selection bits (0 (CVR3:CVR0) 15) REF ) RSRC ) RSRC R/W-0 R/W-0 R/W-0 CVR2 CVR1 CVR0 bit Bit is unknown ) SS 2009 Microchip Technology Inc. ...
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... Section 23.0 “Electrical Characteristics”. TABLE 18-2: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 CVRCON CVREN — CMCON C2OUT C1OUT Legend: Shaded cells are not used with the comparator voltage reference. 2009 Microchip Technology Inc. PIC18F1230/1330 8R CVR3:CVR0 Steps ...
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... PIC18F1230/1330 NOTES: DS39758D-page 186 2009 Microchip Technology Inc. ...
Page 187
... Minimum setting See Table 23-4 in Section 23.0 “Electrical Characteristics” for the specifications. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 The Low-Voltage Detect Control register (Register 19-1) completely controls the operation of the LVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device ...
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... The comparator then generates an interrupt signal by setting the LVDIF bit. The trip point voltage is software programmable to any values. The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). DD LVDL3:LVDL0 LVDCON Register LVDEN Internal Voltage Reference Set LVDIF 2009 Microchip Technology Inc. ...
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... DD LVDIF Enable LVD IRVST Internal reference is stable 2009 Microchip Technology Inc. PIC18F1230/1330 Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked ...
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... Bit 3 Bit 2 IRVST LVDEN LVDL3 LVDL2 INT0IE RBIE TMR0IF — EEIF — LVDIF — EEIE — LVDIE — EEIP — LVDIP Reset Bit 1 Bit 0 Values on Page: LVDL1 LVDL0 48 INT0IF RBIF 47 — — 49 — — 49 — — 49 2009 Microchip Technology Inc. ...
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... Legend: DEVID registers are read-only and cannot be programmed by the user. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up ...
Page 192
... EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39758D-page 192 U-0 R/P-0 R/P-1 — FOSC3 FOSC2 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state 2009 Microchip Technology Inc. R/P-1 R/P-1 FOSC1 FOSC0 bit 0 ...
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... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled See Section 23.1 “DC Characteristics” for the specifications. Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently 2: controlled. 2009 Microchip Technology Inc. PIC18F1230/1330 R/P-1 R/P-1 R/P-1 (1) (1) (2) ...
Page 194
... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39758D-page 194 R/P-1 R/P-1 R/P-1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 WDTPS0 WDTEN bit 0 2009 Microchip Technology Inc. ...
Page 195
... Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states, PWM states Note 1: generated by the Fault inputs or PWM manual override. When PWMPIN = 0, PWMEN<2:0> = 100. PWM output polarity is defined by HPOL and LPOL. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 U-0 R/P-1 R/P-1 ...
Page 196
... Unimplemented: Read as ‘0’ bit 0 FLTAMX: FLTA MUX bit 1 = FLTA is muxed onto RA5 0 = FLTA is muxed onto RA7 DS39758D-page 196 U-0 R/P-0 U-0 — T1OSCMX — Unimplemented bit, read as ‘0’ Unchanged from programmed state 2009 Microchip Technology Inc. U-0 R/P-1 — FLTAMX bit 0 ...
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... Unimplemented: Maintain as ‘0’ bit 2-1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled 2009 Microchip Technology Inc. PIC18F1230/1330 R/P-0 U-0 U-0 BBSIZ0 — — Unimplemented bit, read as ‘0’ ...
Page 198
... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ Unchanged from programmed state 2009 Microchip Technology Inc. R/C-1 R/C-1 CP1 CP0 bit 0 U-0 U-0 — — bit 0 ...
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... Configuration registers are not write-protected 0 = Configuration registers are write-protected bit 4-0 Unimplemented: Read as ‘0’ This bit is read-only in normal execution mode; it can be written only in Program mode. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 U-0 U-0 — — Unimplemented bit, read as ‘0’ ...
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... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ Unchanged from programmed state 2009 Microchip Technology Inc. R/C-1 R/C-1 (1) (1) EBTR1 EBTR0 bit 0 U-0 U-0 — — ...