CDB5376 Cirrus Logic Inc, CDB5376 Datasheet - Page 14

• Manufacturer Part Number: CDB5376
• Description: EVALUATION BOARD FOR CS5376
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5376

• Main Purpose: Seismic Evaluation System
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS3301A, CS3302A, CS4373A, CS5372A, CS5376A
• Primary Attributes: Quad Digital Filter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS330x, CS4373A, CS537x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1778

3. MODULATOR OPERATION
The CS5371A and CS5372A are one- and
two-channel, fourth-order ΔΣ modulators opti-
mized for extremely high-resolution measure-
ment of signals between DC and 2000 Hz.
When combined with CS3301A / CS3302A dif-
ferential amplifiers, the CS4373A test DAC
and CS5376A digital filter, a small, low-power,
self-testing,
measurement system results.
The CS5371A and CS5372A modulators have
high dynamic range and low total harmonic
distortion with very low power consumption
and are optimized for extremely high-resolu-
tion measurement of 5 V
tial signals. They convert analog input signals
from the CS3301A / CS3302A differential am-
plifiers to an oversampled serial bit stream at
512 kbits per second which is then passed to
the digital filter.
The companion CS5376A digital filter gener-
ates the clock and synchronization inputs for
14
INR+
INF+
INF-
INR-
VREF+
VREF-
CS5371A
VA-
VA+
ΔΣ Modulator
4th Order
high-accuracy,
PWDN
OFST
p-p
Figure 10. CS5371A and CS5372A Block Diagrams
or smaller differen-
Generator
multi-channel
Clock
VD
GND
MFLAG
MDATA
MCLK
MSYNC
the CS5371A / CS5372A modulators while re-
ceiving the one-bit data and over-range flag
outputs. The digital filter decimates the modu-
lator’s oversampled output bit stream to a
high-resolution, 24-bit output at the selected
output word rate.
3.1 One’s Density
In normal operation a differential analog input
signal is converted to an oversampled ΔΣ seri-
al bit stream on the MDATA output, with a
one’s density proportional to the differential
amplitude of the analog input signal.
One’s density of the MDATA output is defined
as the ratio of ‘1’ bits to total bits in the serial
bit stream output, i.e. an 86% one’s density
has, on average, a ‘1’ value in 86 of every 100
output data bits. The MDATA output has a
nominal 50% one’s density for a mid-scale dif-
ferential input, approximately 86% one’s den-
sity for a positive full-scale input signal, and
approximately 14% one’s density for a nega-
tive full-scale input signal.
INR1+
INF1+
INF1-
INR1-
VREF+
VREF-
INR2+
INF2+
INF2-
INR2-
VA-
VA+
ΔΣ Modulator
ΔΣ Modulator
4th Order
4th Order
PWDN1
PWDN2
CS5371A CS5372A
OFST
Generator
CS5372A
Clock
VD
GND
DS748F3
MFLAG1
MDATA1
MCLK
MSYNC
MFLAG2
MDATA2