AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 260
![KIT EVAL FOR AT91SAMG45/9M10](/photos/9/21/92142/at91sam9m10-g45-ek_sml.jpg)
AT91SAM9M10-G45-EK
Manufacturer Part Number
AT91SAM9M10-G45-EK
Description
KIT EVAL FOR AT91SAMG45/9M10
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Specifications of AT91SAM9M10-G45-EK
Contents
Board, Cables, Power Supply
Processor To Be Evaluated
AT91SAM9M10
Processor Series
AT91SAM9
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, JTAG
Operating Supply Voltage
5 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Features
Two High Speed USB Hosts, LCD TFT Display
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9M10,
Rohs Compliant
Yes
For Use With/related Products
AT91SAM9M10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
INFINEON
Quantity:
10 000
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
Atmel
Quantity:
135
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22.7.1
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini-
tialize the SDRAM device and to activate deep power-down mode.
260
MODE
000
001
010
011
100
101
110
111
31
23
15
–
–
–
7
–
AT91SAM9M10
DDRSDRC Mode Register
Description
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed
by a write to the SDRAM.
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this
mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a
write to the SDRAM.
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of
the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM.
The write in the SDRAM must be done in the appropriate bank.
Deep power mode: Access to deep power-down mode
Reserved
30
22
14
DDRSDRC_MR
Read-write
See
–
–
–
6
–
Table 22-9
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
6355B–ATARM–21-Jun-10
275.
24
16
–
–
8
–
0
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