AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 44

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6
9.6.1
9.6.2
44
Memory Management Unit (MMU)
AT91SAM9M10
Access Control Logic
Translation Look-aside Buffer (TLB)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir-
tual memory features required by operating systems like Symbian OS
Linux
physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address
(MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The
MMU translates modified virtual addresses to physical addresses by using a single, two-level
page table set stored in physical memory. Each entry in the set contains the access permissions
and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These
entries contain a pointer to either a 1 MB section of physical memory along with attribute infor-
mation (access permissions, domain, etc.) or an entry in the second level translation tables;
coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry
in the coarse table contains a pointer to both large pages and small pages along with access
permissions. An entry in the fine table contains a pointer to large, small and tiny pages.
Table 7 shows the different attributes of each page in the physical memory.
Table 9-6.
The MMU consists of:
The access control logic controls access information for every entry in the translation table. The
access control logic checks two pieces of access information: domain and access permissions.
The domain is the primary access control mechanism for a memory region; there are 16 of them.
It defines the conditions necessary for an access to proceed. The domain determines whether
the access permissions are used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and
for large, small and tiny pages. Sections and tiny pages have a single set of access permissions
whereas large and small pages can be associated with 4 sets of access permissions, one for
each subpage (quarter of a page).
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going
through the translation process every time. When the TLB contains an entry for the MVA (Modi-
Mapping Name
Section
Large Page
Small Page
Tiny Page
• Access control logic
• Translation Look-aside Buffer (TLB)
• Translation table walk hardware
®
. These virtual memory features are memory access permission controls and virtual to
Mapping Details
4K bytes
1K byte
Mapping Size
1M byte
64K bytes
Access Permission By
Section
4 separated subpages
4 separated subpages
Tiny Page
®
, Windows CE
-
-
Subpage Size
16K bytes
1K byte
6355B–ATARM–21-Jun-10
®
, and