AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 39

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.2.6
11.2.7
6462A–ATARM–03-Jun-09
ARM9EJ-S Operating Modes
ARM9EJ-S Registers
Minimum interrupt latency is maintained across both ARM state and Java state. Since byte
codes execution can be restarted, an interrupt automatically triggers the core to switch from
Java state to ARM state for the execution of the interrupt handler. This means that no special
provision has to be made for handling interrupts while executing byte codes, whether in hard-
ware or in software.
In all states, there are seven operation modes:
Mode changes may be made under software control, or may be brought about by external inter-
rupts or exception processing. Most application programs execute in User Mode. The non-user
modes, known as privileged modes, are entered in order to service interrupts or exceptions or to
access protected resources.
The ARM9EJ-S core has a total of 37 registers.
Table 11-1
Table 11-1.
System Mode
• User mode is the usual ARM program execution state. It is used for executing most
• Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data
• Interrupt (IRQ) mode is used for general-purpose interrupt handling
• Supervisor mode is a protected mode for the operating system
• Abort mode is entered after a data or instruction prefetch abort
• System mode is a privileged user mode for the operating system
• Undefined mode is entered when an undefined instruction exception occurs
• 31 general-purpose 32-bit registers
• 6 32-bit status registers
application programs
transfer or channel process
User and
R10
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
shows all the registers in all modes.
ARM9TDMI
Supervisor
Mode
R10
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
™
Modes and Registers Layout
Abort Mode
R10
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Undefined
Mode
R10
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
AT91SAM9G10
Interrupt
Mode
R10
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Interrupt
R10_FIQ
R8_FIQ
R9_FIQ
Mode
Fast
R0
R1
R2
R3
R4
R5
R6
R7
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