AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 654
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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38.9
38.9.1
38.9.2
654
Register Configuration Guide
AT91SAM9G10
STN Mode Example
TFT Mode Example
Once the host has updated the Frame Base Address Registers and the next DMA end of frame
IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the
new backbuffer.
Program the PIO Controller to enable LCD signals.
Enable the LCD controller clock in the Power Management Controller.
PMC_SCER = 1 << 17;//LCDC HCLK = HCK1
STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz
Data rate : 320*240*70*3/8 = 2.016 MHz
HOZVAL= ((3*320)/8 ) - 1
LINEVAL= 240 -1
CLKVAL = (60 MHz/ (2*2.016 MHz)) - 1= 14
LCDCON1= CLKVAL << 12
LCDCON2 = LITTLEENDIAN | SINGLESCAN | STNCOLOR | DISP8BIT| PS8BPP;
LCDTIM1 = 0;
LCDTIM2 = 10 | (10 << 21);
LCDFRMCFG = (HOZVAL << 21) | LINEVAL;
DMAFRMCFG = (7 << 24) + (320 * 240 * 8) / 32;
This example is based on the NEC TFT color LCD module NL6448BC20-08
TFT 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21MHz..29MHz] with a
typical value = 25.175 MHz.
The Master clock must be (2*(n + 1))*pixel clock frequency
HOZVAL = 640 - 1
LINEVAL = 480 - 1
If Master clock is 50 MHz
CLKVAL = (50 MHz/ (2*25.175 MHz)) - 1= 0
VFP = (12 -1), VBP = (31-1), VPW = (2-1), VHDLY= (2-1)
HFP = (16-2), HBP = (48 -1), HPW = (64-1)
LCDCON1= CLKVAL << 12
• Check the DMAFRMPTx register to ensure that there is enough time to update the DMA
• Update the Frame Base Address Registers when the End Of Frame IRQ is generated.
Base Address registers before the end of frame.
.
6462A–ATARM–03-Jun-09
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