EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADUC7128QSPZ
• Description: KIT DEV FOR ADUC7128
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7128QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7128
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SPI Timing Specifications
Table 5. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in the PLLCON MMR, t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
DAV
t
SH
Figure 6. SPI Master Mode Timing (PHASE Mode = 1)
t
DSU
MSB IN
HCLK
2
t
DHD
MSB
= t
t
2
SL
Rev. 0 | Page 11 of 92
UCLK
t
/2
DF
CD
Min
1 × t
2 × t
.
UCLK
UCLK
BIT 6 TO BIT 1
t
DR
BIT 6 TO BIT 1
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
t
SR
HCLK
HCLK
LSB IN
t
SF
ADuC7128/ADuC7129
LSB
Max
2 × t
12.5
12.5
12.5
12.5
HCLK
+ 2 × t
UCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns