EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 84

• Manufacturer Part Number: EVAL-ADUC7128QSPZ
• Description: KIT DEV FOR ADUC7128
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7128QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7128
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7128/ADuC7129
The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region.
Table 121. XMxPAR MMR Bit Designations
Bit
15
14:12
11
10
9
8
7:4
3:0
TIMING DIAGRAMS
Figure 62 through Figure 65 show the timing for a read cycle (see Figure 62), a read cycle with address hold and bus turn cycles (see
Figure 63), a write cycle with address hold and write hold cycles (see Figure 64), and a write cycle with wait states (see Figure 65).
Description
Enable Byte Write Strobe. This bit is only used for two,
8-bit memory sharing the same memory region.
Number of Wait States on the Address Latch Enable Strobe.
Reserved.
Extra Address Hold Time.
Extra Bus Transition Time on Read.
Extra Bus Transition Time on Write.
Number of Write Wait States. Select the number of wait states added to the length of the WS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
Number of Read Wait States. Select the number of wait states added to the length of the RS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
Set by user to gate the AD0 output with the WS output. This allows byte write capability without using BHE and BLE signals.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the read select (RS).
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the write select (WS).
Cleared by user to use BHE and BLE signals.
Set by the user to disable extra hold time.
Cleared by the user to enable one clock cycle of hold on the address in read and write.
AD16:0
HCLK
MSx
AE
RS
ADDRESS
Figure 62. External Memory Read Cycle
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DATA