EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 60
EVAL-ADUC7128QSPZ
Manufacturer Part Number
EVAL-ADUC7128QSPZ
Description
KIT DEV FOR ADUC7128
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7128QSPZ.pdf
(92 pages)
Specifications of EVAL-ADUC7128QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7128
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC7128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- Current page: 60 of 92
- Download datasheet (2Mb)
ADuC7128/ADuC7129
Table 82. COMxIEN0 MMR Bit Designations
Bit
7:4
3
2
1
0
Table 83. COMxIID0 MMR Bit Designations
Bit 2:1
Status Bits
00
11
10
01
00
Table 84. COMxCON1 MMR Bit Designations
Bit
7:5
4
3
2
1
0
Name
RSVD
ETBEI
Name
RSVD
LOOPBACK
RTS
DTR
EDSSI
ELSI
ERBFI
Bit 0
NINT
1
0
0
0
0
Description
Reserved.
Loop Back.
Reserved.
Reserved.
Request to Send.
Data Terminal Ready.
Description
Reserved.
Modem Status Interrupt Enable Bit.
RX Status Interrupt Enable Bit.
Enable Transmit Buffer Empty Interrupt.
Enable Receive Buffer Full Interrupt.
Priority
1
2
3
4
Set by user to enable loop-back mode. In loop-back mode, the SOUT is forced high. In addition, the modem
signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD).
Set by user to force the RTS output to 0.
Cleared by user to force the RTS output to 1.
Set by user to force the DTR output to 0.
Cleared by user to force the DTR output to 1.
Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set.
Cleared by user.
Set by user to enable generation of an interrupt if any of COMxSTA0[3:1] are set.
Cleared by user.
Set by user to enable interrupt when buffer is empty during a transmission.
Cleared by user.
Set by user to enable interrupt when buffer is full during a reception.
Cleared by user.
No Interrupt.
Receive Line Status Interrupt.
Receive Buffer Full Interrupt.
Modem Status Interrupt.
Definition
Transmit Buffer Empty Interrupt.
Rev. 0 | Page 60 of 92
Clearing Operation
Read COMxSTA0.
Read COMxRX.
Write data to COMxTX or read COMxIID0.
Read COMxSTA1.
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