EVAL-ADUC7026QSPZ Analog Devices Inc, EVAL-ADUC7026QSPZ Datasheet - Page 42

• Manufacturer Part Number: EVAL-ADUC7026QSPZ
• Description: KIT DEV ADUC7026/7027 QUICK PLUS
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / Rohs Status: Compliant

ADuC7019/20/21/22/24/25/26/27/28
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the V
of the ADuC7019/20/21/22/24/25/26/27/28. SW2 switches
between A (Channel−) and B (V
connected to ground or a low voltage. The input signal on V
can then vary from V
chosen so that V
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The V
V
Analog Input Structure
Figure 47 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input
signals never exceed the supply rails by more than 300 mV; this
would cause these diodes to become forward-biased and start
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the part.
The C1 capacitors in Figure 47 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors and
typically have a capacitance of 16 pF.
AIN11
AIN11
AIN0
AIN0
V
IN+
IN–
is 0 V to V
MUX
MUX
CHANNEL+
CHANNEL–
CHANNEL+
Figure 45. ADC in Pseudo Differential Mode
IN−
REF
Figure 46. ADC in Single-Ended Mode
REF
CHANNEL–
pin can be floating. The input signal range on
.
+ V
IN−
B
A
A
B
B
A
V
REF
SW1
SW2
SW1
IN−
to V
do not exceed AV
C
C
C
C
REF
S
S
S
S
+ V
REF
). V
IN−
SW3
SW3
. Note that V
IN−
COMPARATOR
COMPARATOR
pin must be
DD
.
IN−
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
must be
DAC
LOGIC
DAC
DAC
LOGIC
DAC
IN−
pin
IN+
Rev. B | Page 42 of 92
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This can necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application. Figure 48 and Figure 49 give an
example of ADC front end.
When no amplifier is used to drive the analog input, the source
impedance should be limited to values lower than 1 kΩ. The
maximum source impedance depends on the amount of total
harmonic distortion (THD) that can be tolerated. The THD
increases as the source impedance increases and the performance
degrades.
DRIVING THE ANALOG INPUTS
Internal or external references can be used for the ADC. In
differential mode of operation, there are restrictions on the
common-mode input signal (V
the reference value and supply voltage used to ensure that the
signal remains within the supply rails. Table 18 gives some
calculated V
Figure 47. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
Figure 48. Buffering Single-Ended/Pseudo Differential Input
CM
V
REF
minimum and V
Figure 49. Buffering Differential Inputs
C1
C1
Track Phase: Switches Closed
AV
AV
10Ω
DD
DD
0.01µF
D
D
D
D
CM
CM
), which is dependent upon
maximum values.
ADuC7019/
ADuC702x
ADC0
ADC1
R1 C2
R1 C2
ADuC7019/
ADuC702x
ADC0