EVAL-ADUC7026QSPZ Analog Devices Inc, EVAL-ADUC7026QSPZ Datasheet - Page 48

• Manufacturer Part Number: EVAL-ADUC7026QSPZ
• Description: KIT DEV ADUC7026/7027 QUICK PLUS
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / Rohs Status: Compliant

ADuC7019/20/21/22/24/25/26/27/28
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiation, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
REMAP Register
Name
REMAP
1
Table 25. REMAP MMR Bit Designations
Bit
4
3
2:1
0
Depends on model.
Name
Remap
Address
0xFFFF0220
Description
Read-Only Bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
Read-Only Bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
Reserved.
Remap Bit. Set by user to remap the SRAM to
Address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
Address 0x00000000.
Default Value
0xXX
1
Access
R/W
Rev. B | Page 48 of 92
RSTSTA Register
Name
RSTSTA
Table 26. RSTSTA MMR Bit Designations
Bit
7:3
2
1
0
RSTCLR Register
Name
RSTCLR
Note that to clear the RSTSTA register, users must write the
Value 0x07 to the RSTCLR register.
Description
Reserved.
Software Reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog Timeout. Set automatically when a
watchdog timeout occurs. Cleared by setting the
corresponding bit in RSTCLR.
Power-On Reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit in
RSTCLR.
Address
0xFFFF0230
Address
0xFFFF0234
Default Value
0x01
Default Value
0x00
Access
R/W
Access
R/W