DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 274

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Interrupt (S12XINTV2)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
1. Please refer to the notes following the PRIOLVL[2:0] description below.
1. Please refer to the notes following the PRIOLVL[2:0] description below.
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime
Write: Anytime
274
Address: 0x012C
Address: 0x012D
Address: 0x012E
Address: 0x012F
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
W
W
R
R
R
R
RQST
RQST
RQST
RQST
0
0
0
0
7
7
7
7
Figure 6-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
Figure 6-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
Figure 6-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
Figure 6-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
0
0
0
0
6
6
6
6
MC9S12XE-Family Reference Manual , Rev. 1.23
5
0
0
5
0
0
5
0
0
5
0
0
0
0
0
0
0
0
0
0
4
4
4
4
0
0
0
0
0
0
0
0
3
3
3
3
2
0
2
0
2
0
2
0
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
Freescale Semiconductor
0
0
0
0
1
1
1
1
1
1
1
1
0
(1)
0
(1)
0
(1)
0
(1)